A3PN125-ZVQG100 Actel, A3PN125-ZVQG100 Datasheet - Page 8

FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano


Manufacturer Part Number
FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

Specifications of A3PN125-ZVQG100

Processor Series
IP Core
Number Of Macrocells
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
Data Ram Size
36 Kbit
Delay Time
1.02 ns
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
Supply Voltage (min)
1.5 V
Number Of Gates
125 K
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ProASIC3 nano Device Overview
to make invasive attacks extremely difficult. ProASIC3 nano devices, with FlashLock and AES security,
are unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is
protected and secure, making remote ISP possible. A ProASIC3 nano device provides the most
impenetrable security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3 nano
FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load
device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and
system reliability.
Live at Power-Up
Actel flash-based ProASIC3 nano devices support Level 0 of the LAPU classification standard. This
feature helps in system component initialization, execution of critical tasks before the processor wakes
up, setup and configuration of memory blocks, clock generation, and bus activity management. The
LAPU feature of flash-based ProASIC3 nano devices greatly simplifies total system design and reduces
total system cost, often eliminating the need for CPLDs and clock generation PLLs that are used for
these purposes in a system. In addition, glitches and brownouts in system power will not corrupt the
ProASIC3 nano device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to
be reloaded when system power is restored. This enables the reduction or complete removal of the
configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from
the PCB design. Flash-based ProASIC3 nano devices simplify total system design and reduce cost and
design risk while increasing system reliability and improving system initialization time.
Firm Errors
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike
a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These
errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a
complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 nano flash-
based FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 nano FPGAs
cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors
occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection
and correction (EDAC) circuitry built into the FPGA fabric.
Low Power
Flash-based ProASIC3 nano devices exhibit power characteristics similar to an ASIC, making them an
ideal choice for power-sensitive applications. ProASIC3 nano devices have only a very limited power-on
current surge and no high-current transition period, both of which occur on many FPGAs.
ProASIC3 nano devices also have low dynamic power consumption to further maximize power savings.
Advanced Flash Technology
ProASIC3 nano devices offer many benefits, including nonvolatility and reprogrammability through an
advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design
techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization
without compromising device routability or performance. Logic functions within the device are
interconnected through a four-level routing hierarchy.
Advanced Architecture
The proprietary ProASIC3 nano architecture provides granularity comparable to standard-cell ASICs.
The ProASIC3 nano device consists of five distinct and programmable architectural features
Figure 1-4 on page
FPGA VersaTiles
1 - 2
R e vi s i o n 8
(Figure 1-3

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