A3PN060-ZVQG100 Actel, A3PN060-ZVQG100 Datasheet - Page 24

• Manufacturer Part Number: A3PN060-ZVQG100
• Description: FPGA - Field Programmable Gate Array 60K System Gates ProASIC3 nano
• Manufacturer: Actel

Specifications of A3PN060-ZVQG100

• Processor Series: A3PN060
• Core: IP Core
• Number Of Macrocells: 512
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 71
• Data Ram Size: 18 Kbit
• Delay Time: 0.96 ns
• Supply Voltage (max): 3.3 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Development Tools By Supplier: AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 60 K
• Package / Case: VQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ProASIC3 nano DC and Switching Characteristics
2- 10
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula by adding its corresponding contribution (P
Combinatorial Cells Contribution—P
Routing Net Contribution—P
I/O Input Buffer Contribution—P
I/O Output Buffer Contribution—P
RAM Contribution—P
PLL Contribution—P
P
N
α
F
P
N
N
α
F
P
N
α
F
P
N
α
β
F
P
N
F
β
F
β
P
F
CLK
CLK
CLK
CLK
READ-CLOCK
WRITE-CLOCK
CLKOUT
C-CELL
NET
INPUTS
OUTPUTS
MEMORY
PLL
C-CELL
S-CELL
C-CELL
INPUTS
OUTPUTS
1
BLOCKS
2
3
1
1
2
2
is the I/O buffer enable rate—guidelines are provided in
is the RAM enable rate for read operations.
is the RAM enable rate for write operations—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
= P
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
= (N
= N
is the number of VersaTiles used as combinatorial modules in the design.
is the number of VersaTiles used as sequential modules in the design.
is the number of VersaTiles used as combinatorial modules in the design.
= N
DC4
is the number of I/O input buffers used in the design.
is the output clock frequency.
is the number of RAM blocks used in the design.
S-CELL
= P
= N
is the number of I/O output buffers used in the design.
C-CELL
INPUTS
+ P
AC11
is the memory read clock frequency.
OUTPUTS
is the memory write clock frequency.
AC13
+ N
*
* N
*
α
C-CELL
α
PLL
*F
BLOCKS
1
MEMORY
2
/ 2 * P
*
CLKOUT
/ 2 * P
α
) *
2
/ 2 *
AC7
* F
α
NET
AC9
1
READ-CLOCK
β
/ 2 * P
* F
INPUTS
* F
1
CLK
* P
OUTPUTS
CLK
1
AC8
AC10
C-CELL
R e visio n 8
* F
* F
*
AC14
CLK
β
CLK
2
+ P
* F
CLKOUT
AC12
* N
Table 2-12 on page
Table 2-12 on page
Table 2-13 on page
product) to the total PLL contribution.
BLOCK
* F
Table 2-12 on page
Table 2-12 on page
WRITE-CLOCK
Table 2-13 on page
2-11.
2-11.
2-11.
*
β
3
2-11.
2-11.
2-11.