LFE2M20SE-5FN484C Lattice, LFE2M20SE-5FN484C Datasheet
LFE2M20SE-5FN484C
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LFE2M20SE-5FN484C Summary of contents
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... LatticeECP2/M Family Data Sheet DS1006 Version 03.8, April 2011 ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... The Diamond and ispLEVER tools use the synthesis tool output along with the con- straints from its floor planning tools to place and route the design in the LatticeECP2/M device. The Diamond and ispLEVER tools extract the timing from the routing and back-annotates it into the design for timing verification. ...
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... The LatticeECP2/M devices use 1.2V as their core voltage. © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... DSP Blocks Multiply & Accumulate Support Configuration Logic, Including dual boot and encryption, and soft-error detection sysMEM Block RAM 18kbit Dual Port On-Chip Oscillator LatticeECP2/M Family Data Sheet Channel Channel Channel Channel 2-2 Architecture Flexible sysIO Buffers: LVCMOS, HSTL, SSTL, ...
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... Lattice Semiconductor PFU Blocks The core of the LatticeECP2/M device consists of PFU blocks, which are provided in two forms, the PFU and PFF. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remain- der of this data sheet will use the term PFU to refer to both PFU and PFF blocks ...
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... F0, F1 LUT4 output register bypass signals Q0, Q1 Register outputs OFX0 Output of a LUT5 MUX OFX1 Output of a LUT6, LUT7, LUT8 FCO Slice 2 of each PFU is the fast carry chain output 2-4 LatticeECP2/M Family Data Sheet SLICE OFX1 FF* To Routing LUT5 Mux ...
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... PFU. Table 2-3 shows the number of slices required to implement different distributed RAM primitives. For more information about using RAM in LatticeECP2/M devices, please see the list of additional technical documentation at the end of this data sheet. ...
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... ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in ROM mode. Preloading is accomplished through the programming interface during PFU configuration. Routing There are many resources provided in the LatticeECP2/M devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. ...
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... These signals are not available in SPLL. Dynamic Delay Adjustment Voltage Delay Controlled Adjust Oscillator PLLCAP External Pin (Optional External Capacitor) Description 2-7 Architecture LatticeECP2/M Family Data Sheet Dynamic Adjustment Post Scalar Phase/Duty Divider Select (CLKOP) Secondary Divider (CLKOK) LOCK CLKOS CLKOP ...
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... The user can configure the DLL for many common functions such as time reference delay mode and clock injection removal mode. Lattice provides primitives in its design tools for these functions. For more information about the DLL, please see the list of additional technical documentation at the end of this data sheet. ...
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... CLKFB_CK CLKOP GDLLFB_PIO ECLK1 * Software selectable PLL/DLL Cascading LatticeECP2/M devices have been designed to allow certain combinations of PLL (GPLL and SPLL) and DLL cas- cading. The allowable combinations are: • PLL to PLL supported • PLL to DLL supported LatticeECP2/M Family Data Sheet Description ...
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... SPLL_PIO Clock Dividers LatticeECP2/M devices have two clock dividers, one on the left side and one on the right side of the device. These are intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷4 or ÷8 mode and maintains a known phase relationship between the divided down clock and the high-speed clock based on the release of its reset signal ...
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... DLLs, located on the left and right sides of the device. There are eight dedicated clock inputs, two on each side of the device, with the exception of the LatticeECP2M 256-fpBGA package devices which have six dedicated clock inputs on the device. Figure 2-10 shows the primary clock sources. ...
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... Clock Input DLL Input DLL PLL Input GPLL Note: This diagram shows sources for the ECP2-50 device. Smaller LatticeECP2 devices have fewer SPLLs. All LatticeECP2M device have six SPLLs. LatticeECP2/M Family Data Sheet Clock Input Clock Input From Routing Primary Clock Sources ...
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... Lattice Semiconductor Secondary Clock/Control Sources LatticeECP2/M devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads and the rest from routing. Figure 2-11 shows the secondary clock sources. Figure 2-11. Secondary Clock Sources From Routing From Routing From Routing ...
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... Clock Input From Routing DLLDELA DLL DLL Input PLL GPLL Input Sources for left edge clocks LatticeECP2/M Family Data Sheet Clock Input Clock Input From From Routing Routing Sources for top edge clocks Eight Edge Clocks (ECLK) Two Clocks per Edge ...
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... Lattice Semiconductor Primary Clock Routing The clock routing structure in LatticeECP2/M devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center of the device. All the clock sources are connected to these muxes. Figure 2-13 shows the clock routing for one quadrant ...
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... Lattice Semiconductor this special vertical routing channel and the eight secondary clock regions for the ECP2-50. LatticeECP2 devices have four secondary clocks (SC0 to SC3) which are distrubed to every region. The secondary clock muxes are located in the center of the device. Figure 2-16 shows the mux structure of the secondary clock routing ...
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... Secondary Clock Feedlines: 8 PIOs + 16 Routing 24:1 24:1 24:1 24:1 SC1 SC2 SC3 SC4 Clock/Control 4 High Fan-out Data Signals (SC4 to SC7) per Region Primary Clock 8 4 25:1 Routing 12 Vcc 1 2-17 Architecture LatticeECP2/M Family Data Sheet 24:1 24:1 24:1 SC5 SC6 SC7 High Fan-out Data Clock to Slice ...
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... Secondary Clock Edge Clock Routing LatticeECP2/M devices have a number of high-speed edge clocks that are intended for use with the PIOs in the implementation of high-speed interfaces. There are eight edge clocks per device: two edge clocks per edge. Differ- ent PLL and DLL outputs are routed to the two muxes on the left and right sides of the device. In addition, the CLKO signal (generated from the DLLDELA block) is routed to all the edge clock muxes on the left and right sides of the device ...
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... ROM. Memory Cascading Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual and Pseudo-Dual Port Modes In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array ...
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... EBR synchronous reset setup time before the next active read or write clock edge. Memory Core Output Data Programmable Disable Reset Clock Clock Enable 2-20 Architecture LatticeECP2/M Family Data Sheet SET Q Port A[17: CLR Latches SET Port B[17:0] ...
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... The user selects a function element for a DSP block and then selects the width and type (signed/unsigned) of its operands. The operands in the LatticeECP2/M family sysDSP Blocks can be either signed or unsigned but not mixed within a function element. Similarly, the operand widths cannot be mixed within a block. In the LatticeECP2/ M family the DSP elements can be concatenated ...
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... In the ‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle. • In the ‘Add/Sub’ option the Accumulator can be switched between addition and subtraction on every cycle. • The loading of operands can switch between parallel and serial operations. LatticeECP2/M Family Data Sheet x9 x18 ...
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... Multiplicand Multiplier n Input Data Register B Signed A Signed B Shift Register B Out Shift Register Multiplier Input Data m Register Input To Register Multiplier Input To Register Multiplier Shift Register A Out 2-23 Architecture LatticeECP2/M Family Data Sheet m+n m+n (default) x Output Pipeline Register CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) ...
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... The output register is used to store the accumulated value. The Accumulators in the DSP blocks in the LatticeECP2/M family can be initialized dynamically. A registered overflow signal is also avail- able. The overflow conditions are provided later in this document. Figure 2-24 shows the MAC sysDSP element. ...
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... To Add/Sub Register Register Reg Input Pipeline Pipe To Add/Sub Register Register Reg Input Pipeline Pipe To Add/Sub Register Register Reg Shift Register A Out 2-25 Architecture LatticeECP2/M Family Data Sheet CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) m+n (default) Add/Sub Output m+n+1 m+n+1 (default) (default) m+n (default) ...
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... To Add/Sub0, Add/Sub1 Register Register Input Pipeline To Add/Sub0, Add/Sub1 Register Register Input Pipeline To Add/Sub0 Register Register Input Pipeline To Add/Sub1 Register Register Shift Register A Out 2-26 Architecture LatticeECP2/M Family Data Sheet CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) Add/Sub0 m+n+1 SUM m+n+2 m+n+2 m+n+1 Add/Sub1 Output ...
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... Signed Operation 2-27 Architecture LatticeECP2/M Family Data Sheet Two’s Complement Two’s Complement Signed 9 Bits Signed 18 Bits 000000101 000000000000000101 111111010 111111111111111010 3 2 Carry signal is generated for 1 one cycle when this ...
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... DSP design cycle in Lattice FPGAs. Optimized DSP Functions Lattice provides a library of optimized DSP IP functions. Some of the IP cores planned for the LatticeECP2/M DSP include the Bit Correlator, Fast Fourier Transform, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/ Decoder, Turbo Encoder/Decoder and Convolutional Encoder/Decoder ...
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... Each PIC contains two PIOs connected to their respective sysI/O buffers as shown in Figure 2-28. The PIO Block supplies the output data (DO) and the tri-state control signal (TO) to the sysI/O buffer and receives input from the buffer. Table 2-12 provides the PIO signal list. LatticeECP2/M Family Data Sheet DSP Performance DSP Block ...
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... The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as inputs. LatticeECP2/M Family Data Sheet PIOA IOLT0 ...
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... DQS signal, creating two data streams, D0 and D1. These two data streams are synchronized with the system clock before entering the core. Further discussion on this topic is in the DDR Memory section of this data sheet. LatticeECP2/M Family Data Sheet Description Clock enables for input and output block flip-flops ...
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... D-Type DDRSRC SDR & Sync DDR Registers Registers D-Type D-Type D-Type Gearbox Configuration Bit 2-32 Architecture LatticeECP2/M Family Data Sheet INCK** To DQS Delay Block** INDD Clock Transfer Registers IPOS0A QPOS0A D-Type /LATCH D-Type* IPOS1A QPOS1A D-Type D-Type* /LATCH To Routing INCK** To DQS Delay Block** ...
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... ONEG0A, ONEG1A, ONEG1B and ONEG1B. Figure 2-32 shows the diagram using this gearbox function. For more information about this topic, please see infor- mation regarding additional documentation at the end of this data sheet. LatticeECP2/M Family Data Sheet D Q ...
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... Clock Transfer Registers ECLK1 ECLK2 CLK1 (CLKB) DQSXFER * Shared with input register Latch Latch Note: Simplified version does not show CE and SET/RESET details 2-34 Architecture LatticeECP2/M Family Data Sheet D-Type 1 /LATCH D-Type Latch DDR Output D Q Registers D-Type /LATCH D-Type Latch ...
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... PICs on the bottom edge have registered elements that support DDR memory interfaces. One of every 18 PIOs contains a delay element to facilitate the generation of DQS signals. The DQS signal feeds the DQS bus that spans the set of 18 PIOs. Figure 2-34 shows the assignment of DQS pins in each set of 18 PIOs. LatticeECP2/M Family Data Sheet Q D ...
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... Figure 2-33. DQS Input Routing for the Left and Right Edges of the Device DQS LatticeECP2/M Family Data Sheet PADA "T" PIO A LVDS Pair PADB "C" ...
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... DLLs (DDR_DLL) on opposite sides of the device. Each DLL compensates DQS delays in its half of the device as shown in Figure 2-35. The DLL loop is compensated for temperature, volt- age and process variations by the system clock and feedback loop. LatticeECP2/M Family Data Sheet PADA "T" PIO A LVDS Pair PADB " ...
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... Figure 2-35. Edge Clock, DLL Calibration and DQS Local Bus Distribution Spans 16 PIOs I DQS Input 7 I Spans 18 PIOs Note: Bank 8 is not shown. LatticeECP2/M Family Data Sheet I/O Bank 0 I/O Bank 1 DDR_DLL DDR_DLL (Right) (Left) I/O Bank 4 I/O Bank 5 2-38 Architecture ECLK1 ECLK2 I ...
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... In a typical DDR Memory interface design, the phase relationship between the incoming delayed DQS strobe and the internal system clock (during the READ cycle) is unknown. The LatticeECP2/M family contains dedicated circuits to transfer data between these domains. To prevent set-up and hold violations, at the domain transfer between DQS (delayed) and the system clock, a clock polarity selector is used ...
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... Lattice Semiconductor DQSXFER LatticeECP2/M devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memo- ries that require DQS strobe be shifted 90 DQSXFER signal runs the span of the data bus. sysI/O Buffer Each I/O is associated with a flexible buffer referred sysI/O buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement the wide variety of standards that are found in today’ ...
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... Lattice Semiconductor Figure 2-37. LatticeECP2 Banks V CCIO7 V REF1(7) V REF2(7) GND V CCIO6 V REF1(6) V REF2(6) GND LatticeECP2/M Family Data Sheet TOP Bank 0 Bank 1 Bank 5 Bank 4 BOTTOM 2-41 Architecture V CCIO2 V REF1(2) V REF2(2) GND V CCIO3 V REF1(3) V REF2(3) GND V CCIO8 GND ...
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... V REF1(6) V REF2(6) GND LatticeECP2/M devices contain two types of sysI/O buffer pairs. 1. Top (Bank 0 and Bank 1) sysI/O Buffer Pairs (Single-Ended Outputs Only) The sysI/O buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be con- figured as a differential input. ...
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... In LatticeECP2 devices, only the I/Os on the bottom banks have programmable PCI clamps. In LatticeECP2M devices, the I/Os on the left and bottom banks have programmable PCI clamps. ...
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... Lattice Semiconductor O standards (together with their supply and reference voltages) supported by LatticeECP2/M devices. For further information about utilizing the sysI/O buffer to support a variety of standards please see the the list of additional technical information at the end of this data sheet. Table 2-13. Supported Input Standards ...
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... During power-up and power-down sequences, the I/Os remain in tri-state until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits. This allows for easy integration with the rest of the system. These capabilities make the LatticeECP2/M ideal for many multiple power supply and hot-swap applications. ...
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... SERDES and PCS (Physical Coding Sublayer) LatticeECP2M devices feature channels of embedded SERDES arranged in quads at the corners of the devices. Figure 2-39 shows the position of the quad blocks in relation to the PFU array for LatticeECP2M70 and LatticeECP2M100 devices. Table 2-15 shows the location of Quads for all the devices. ...
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... Popular standards such as 10Gb Ethernet and x4 PCI-Express and 4x Serial RapidIO can be implemented using IP (provided by Lattice), a single quad (Four SERDES channels and PCS) and some additional logic from the core. For further information about SERDES, please see the list of additional technical documentation at the end of this data sheet ...
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... AES encrypted bitstream, securing designs and deterring design piracy. 2. TransFR (Transparent Field Reconfiguration) TransFR I/O (TFR unique Lattice technology that allows users to update their logic in the field without interrupting system operation using a single ispVM ing device configuration. This allows the device to be field updated with a minimum of system disruption and downtime ...
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... Software default frequency. Density Shifting The LatticeECP2/M family is designed to ensure that different density devices in the same family and in the same package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases also possible to shift a lower uti- lization design targeted for a high-density device to a lower density device ...
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... Transmit Power Supply CCTX © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min. Max. 1.14 1. set to 3.3V, they must be con- CC. CCIO CCJ through careful filtering and CC CC CCIO8 (LatticeECP2/M “S” version devices only). SERDES. Min. Typ. Max. — — +/-1000 — — 4 Units CCAUX , the V ...
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... V = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, CCIO V = 1.2V (MAX 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, CCIO V = 1.2V (MAX 3-3 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min. Typ. Max. — — 10 — — 150 -30 — -210 30 — 210 30 — — -30 — — — ...
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... Over Recommended Operating Conditions Parameter ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70 ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70 ECP2-35, -50, -70 Only ECP2-35, -50, -70 Only ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70 All Devices 3-4 DC and Switching Characteristics LatticeECP2/M Family Data Sheet 5 Device Typ 100 0.5 0 GND ...
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... Over Recommended Operating Conditions Parameter ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100 ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100 All Devices All Devices ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100 All Devices 3-5 DC and Switching Characteristics LatticeECP2/M Family Data Sheet 5 Device Typ 100 100 0.5 0 GND. CCIO ...
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... Over Recommended Operating Conditions ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70 ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70 ECP2-35, -50, -70 Only ECP2-35, -50, -70 Only All Devices All Devices 3-6 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Device Typ 135 187 267 0.5 0 GND ...
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... Values shown in this column are the typical average DC current during configuration. Use the Power Calculator tool to find the peak startup current Over Recommended Operating Conditions Parameter 3-7 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Device Typ. ECP2M20 41 ECP2M35 107 ECP2M50 ...
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... Lattice Semiconductor SERDES Power Supply Requirements (LatticeECP2M Family Only) Symbol Standby (Power Down current (per channel) CCTX-SB CCTX I V current (per channel) CCRX-SB CCRX I Input buffer current (per channel) CCIB-SB I Output buffer current (per channel) CCOB-SB I SERDES PLL current (per quad) ...
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... HSTL15D_ I 1.425 2 2 HSTL18D_ 1.71 1. Inputs on chip. Outputs are implemented with the addition of external resistors. 2. Input on this standard does not depend on the value and Switching Characteristics LatticeECP2/M Family Data Sheet V CCIO Typ. Max. Min. 3.3 3.465 2.5 2.625 1.8 1.89 1 ...
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... REF - 0.125 V + 0.125 3.6 REF - 0.125 V + 0.125 3.6 REF - 0 0.1 3.6 REF - 0 0.1 3.6 REF - 0 0.1 3.6 REF 3-10 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Max. (V) Min. (V) I (mA) OL 20, 16, 0 0.4 CCIO 12 0 0.2 0.1 CCIO 20, 16, 0 0.4 CCIO 12 ...
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... Ohm )/ 100 Ohm Driver Outputs Shorted to OD Ground Driver Outputs Shorted to OD Each Other 3-11 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min. Typ. Max. 0 — 2.4 0.05 — 2.35 +/-100 — — — — +/-10 — 1.38 1.60 0.9V 1.03 — ...
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... Lattice Semiconductor LVDS25E The top and bottom sides of LatticeECP2/M devices support LVDS outputs via emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possible solution for point-to-point signals. Figure 3-1. LVDS25E Output Termination Example VCCIO = 2.5V (± ...
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... Lattice Semiconductor BLVDS The LatticeECP2/M devices support the BLVDS standard. This standard is emulated using complementary LVC- MOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals ...
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... Lattice Semiconductor LVPECL The LatticeECP2/M devices support the differential LVPECL standard. This standard is emulated using comple- mentary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input stan- dard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point-to-point signals ...
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... Lattice Semiconductor RSDS The LatticeECP2/M devices support differential RSDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup- ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation ...
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... Lattice Semiconductor MLVDS The LatticeECP2/M devices support the differential MLVDS standard. This standard is emulated using complemen- tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for MLVDS standard implementation ...
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... Distributed Memory Functions 16x4 Pseudo-Dual Port RAM (One PFU) 32x4 Pseudo-Dual Port RAM 64x8 Pseudo-Dual Port RAM DSP Functions 18x18 Multiplier (All Registers) 9x9 Multiplier (All Registers) DC and Switching Characteristics LatticeECP2/M Family Data Sheet 1 -7 Timing 3.8 4.5 5.0 3.2 3.4 3 ...
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... Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The Diamond or ispLEVER design tools can provide logic timing numbers at a particular temperature and voltage. DC and Switching Characteristics LatticeECP2/M Family Data Sheet -7 Timing 372 295 ...
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... LFE2-35 1.40 LFE2-50 1.40 LFE2-70 1.40 LFE2M20 1.40 LFE2M35 1.40 LFE2M50 1.80 LFE2M70 1.80 LFE2M100 1.80 3-19 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Max. Min. Max. Min. Max. 3.50 — 3.90 — 3.50 — 3.90 — 3.50 — 3.90 — ...
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... LFE2-35 — LFE2-50 — LFE2-70 — LFE2M20 — LFE2M35 — LFE2M50 — LFE2M70 — LFE2M100 — 3-20 DC and Switching Characteristics LatticeECP2/M Family Data Sheet 9 (Continued Max. Min. Max. Min. Max. — 1.70 — 1.90 — 1.70 — 1.90 — 1.70 — ...
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... LFE2-35 1.00 LFE2-50 1.00 LFE2-70 1.00 LFE2M20 1.20 LFE2M35 1.20 LFE2M50 1.20 LFE2M70 1.20 LFE2M100 1.20 3-21 DC and Switching Characteristics LatticeECP2/M Family Data Sheet 9 (Continued Max. Min. Max. Min. Max. — 0.00 — 0.00 — 0.00 — 0.00 — 0.00 — ...
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... LFE2-35 0.70 LFE2-50 0.70 LFE2-70 0.70 LFE2M20 0.70 LFE2M35 0.70 LFE2M50 0.70 LFE2M70 0.70 LFE2M100 0.80 3-22 DC and Switching Characteristics LatticeECP2/M Family Data Sheet 9 (Continued Max. Min. Max. Min. Max. — 0.00 — 0.00 — 0.00 — 0.00 — 0.00 — ...
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... LFE2M70 0.00 LFE2M100 0.00 ECP2/M — ECP2/M 0.640 0.250 ECP2/M 0.250 ECP2/M 95 ECP2/M — ECP2/M 0.640 3-23 DC and Switching Characteristics LatticeECP2/M Family Data Sheet 9 (Continued Max. Min. Max. Min. — 1.20 — 1.40 — 1.20 — 1.40 — 1.20 — ...
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... ECP2-35 — ECP2-50 — ECP2-70 — ECP2M20 — ECP2M35 — ECP2M50 — ECP2M70 — ECP2M100 — 3-24 DC and Switching Characteristics LatticeECP2/M Family Data Sheet 9 (Continued Max. Min. Max. Min. Max. — 0.250 — 0.250 — 0.250 — 0.250 266 133 ...
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... ECP2/M 960 ECP2/M 960 ECP2/M — 0.95 ECP2/M — ECP2/M — ECP2/M 0.95 ECP2/M — for best performance. 3-25 DC and Switching Characteristics LatticeECP2/M Family Data Sheet 9 (Continued Max. Min. Max. Min. Max. 280 — 280 — 280 — 280 — 280 — ...
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... Lattice Semiconductor Figure 3-6. SPI4.2 Parameters t DIBSPI CLK Data (TDAT, TCTL) t DIASPI RDTCLK Data (RDAT,RCTL) t DVACLKSPI Transmit Parameters t DIASPI t DIBSPI Receiver Parameters t DVACLKSPI t t DVECLKSPI DVECLKSPI 3-26 DC and Switching Characteristics LatticeECP2/M Family Data Sheet ...
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... DQS DQ t DVADQ Figure 3-8. XGMII Parameters CLOCK DATA t DVBCKXGMII t DVACKXGMII CLOCK DATA t SUXGMII t HXGMII Transmit Parameters t DQVAS t DQVBS Receiver Parameters t DVADQ t t DVEDQ DVEDQ Transmit Parameters t DVACKXGMII t DVBCKXGMII Receiver Parameters t SUXGMII t HXGMII 3-27 DC and Switching Characteristics LatticeECP2/M Family Data Sheet ...
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... DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min. Max. Min. Max. — 0.198 — 0.216 — 0.331 — 0.358 — 0.655 — 0.711 — ...
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... AddSub Input Register Setup Time SUADDSUB t AddSub Input Register Hold Time HADDSUB 1. Internal parameters are characterized but not tested on every device. 2. These parameters apply to LatticeECP devices only. 3. DSP Block is configured in Multiply Add/Sub 18x18 Mode. Over Recommended Operating Conditions -7 Min. Max. 0.139 ...
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... Figure 3-10. Read/Write Mode with Input and Output Registers CLKA CSA WEA ADA t DIA DOA (Regs CO_EBR Mem(n) data from previous read output is only updated during a read cycle 3-30 DC and Switching Characteristics LatticeECP2/M Family Data Sheet CO_EBR CO_EBR COO_EBR COO_EBR D1 D0 ...
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... Data from Prev Read DOA or Write Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Three consecutive writes ACCESS ACCESS ACCESS D0 D1 3-31 DC and Switching Characteristics LatticeECP2/M Family Data Sheet ACCESS ...
Page 84
... HSTL_18 class I 8mA drive HSTL18_II HSTL_18 class II HSTL18D_I Differential HSTL 18 class I 8mA drive HSTL18D_II Differential HSTL 18 class Over Recommended Operating Conditions Description 3-32 DC and Switching Characteristics LatticeECP2/M Family Data Sheet - -0.04 -0.02 0.00 -0.04 -0.09 -0.15 -0.15 -0.15 -0.15 -0.15 -0.15 -0.15 ...
Page 85
... LVCMOS 3.3 12mA drive, slow slew rate LVCMOS33_16mA LVCMOS 3.3 16mA drive, slow slew rate LVCMOS33_20mA LVCMOS 3.3 20mA drive, slow slew rate (Continued) Over Recommended Operating Conditions Description 3-33 DC and Switching Characteristics LatticeECP2/M Family Data Sheet - -0.22 -0.25 -0.27 -0.22 -0.25 -0.27 -0.12 -0 ...
Page 86
... LVCMOS timing measured with the load specified in Switching Test Condition table. 3. All other standards tested according to the appropriate specifications. 4. These timing adders are measured with the recommended resistor values. Timing v.A 0. (Continued) Over Recommended Operating Conditions Description 3-34 DC and Switching Characteristics LatticeECP2/M Family Data Sheet - 2.18 2.26 2.33 2.19 2.35 2.51 1 ...
Page 87
... MHz OUT f < 50 MHz OUT N/M = integer At 90% or 10% Without external capacitor With external capacitor 90% to 90% 10% to 10% Without external capacitor With external capacitor 3-35 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min. Typ. Max. 20 — 420 — 420 20 — 420 5 5 — ...
Page 88
... OUT f < 50 MHz OUT Divider Ratio = Integer At 90% or 10% Without external capacitor With external capacitor 90% to 90% 10% to 10% Without external capacitor With external capacitor 3-36 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min. Typ. Max. 33 — 420 — 420 33 — 420 ...
Page 89
... CLKOP runs at the same frequency as the input clock. 2. CLKOS minimum frequency is obtained with divide This is intended “path-matching” design guideline and is not a measurable specification. Over Recommended Operating Conditions Description 3-37 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min. Typ. Max. 100 — 500 100 — ...
Page 90
... Lattice Semiconductor SERDES High-Speed Data Transmitter (LatticeECP2M Family Only) Table 3-7. Serial Output Timing and Levels Symbol Description Differential swing (1V setting) V TX-DIFF-P-P-1 Differential swing (1.25V setting) V TX-DIFF-P-P-1.25 Differential swing (1.3V setting) V TX-DIFF-P-P-1.3 Differential swing (1.35V setting) V TX-DIFF-P-P-1.35 Output common mode voltage ...
Page 91
... DC and Switching Characteristics LatticeECP2/M Family Data Sheet Max. Units 0.12 UI, p-p 0.51 UI, p-p 0.59 UI, p-p 0.19 UI, p-p 0.34 UI, p-p 0.45 UI, p-p 0.11 UI, p-p 0.22 UI, p-p 0.28 UI, p-p Max ...
Page 92
... Recovered Clock Deserializer Polarity 1:8/1:10 Adjust BYPASS BYPASS T3 Encoder Polarity Adjust BYPASS BYPASS 3-40 DC and Switching Characteristics LatticeECP2/M Family Data Sheet FPGA Core PCS FPGA Bridge FPGA EBRD Clock DEC Elastic Buffer Down Receive Data FIFO Sample FIFO BYPASS BYPASS FPGA ...
Page 93
... Lattice Semiconductor SERDES High Speed Data Receiver (LatticeECP2M Family Only) Table 3-11. Serial Input Data Specifications Symbol Description Stream of nontransitions RX-CID S (CID = Consecutive Identical Digits Differential input sensitivity RX-DIFF-S V Input levels RX-IN V Input common mode range (DC coupled) RX-CM-DC V Input common mode range (AC coupled) ...
Page 94
... Values are measured with PRBS 2 -1, all channels operating. 2. Jitter specification is limited by measurement equipment capability. 1 Condition Min. — — — — 3-42 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Typ. Max. — 0.20 — 0.22 — 0.20 — 0.08 Units UI, p-p ...
Page 95
... Lattice Semiconductor SERDES External Reference Clock (LatticeECP2M Family Only) The external reference clock selection and its interface are a critical part of system applications for this product. Table 3-14 specifies reference clock requirements, over the full range of operating conditions. Table 3-14. External Reference Clock Specification (refclkp/refclkn) ...
Page 96
... DC input impedance RX- Power-down DC input impedance RX-HIGH-IMP-DC T Receiver eye width RX-EYE T RX-EYE-MEDIAN-TO-MAX-JITTER Notes: 1. Measured with external AC-coupling on the receiver 2. Values are measured at 2.5 Gbps DC and Switching Characteristics LatticeECP2/M Family Data Sheet Description Test Conditions V =0.0V TX-D+ V =0.0V TX- 80 80% Description Test Conditions 3-44 Min ...
Page 97
... Clock input rise/fall time Differential input voltage swing SW DC Input clock duty cycle REFCLK PPM Reference clock tolerance Description Test Conditions 3-45 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min. Typ. Max. — 100 — — 0.65 — — — 1.0 0.6 — ...
Page 98
... Lattice Semiconductor LatticeECP2/M sysCONFIG Port Timing Specifications Parameter sysCONFIG Byte Data Flow t Byte D[0:7] Setup Time to CCLK SUCBDI t Byte D[0:7] Hold Time to CCLK HCBDI t CCLK to DOUT in Flowthrough Mode CODO t CSN[0:1] Setup Time to CCLK SUCS t CSN[0:1] Hold Time to CCLK HCS t Write Signal Setup Time to CCLK ...
Page 99
... Lattice Semiconductor LatticeECP2/M sysCONFIG Port Timing Specifications (Continued) Parameter t SOSPI Data Setup Time Before CCLK SUSPI t SOSPI Data Hold Time After CCLK HSPI 1. Re-toggling the PROGRAMN pin is not permitted until the INITN pin is high. Avoid consecutive toggling of the PROGRAMN. 2. For SED (Soft Error Detect), the SEDCLKIN operating frequency must be at least 20MHz. SEDCLKIN is derived from Master Clock Fre- quency that has a +/-30% variation ...
Page 100
... SUWD t t HCBDI SUCBDI Byte 0 Byte 1 t SSCL t SUSCDI t ICFG t VMC t SUCFG Valid whichever is the last to reach its V CC CCAUX 3-48 DC and Switching Characteristics LatticeECP2/M Family Data Sheet t BSCYC t BSCH t HCS t HWD t DCB Byte 2 Byte n t SSCH t HSCDI t CODO t HCFG . MIN ...
Page 101
... DINIT INITN t CSSPI t CSSPI[0:1]N CFGX CCLK SISPI/BUSY D7/SPID0 t PRGM t IODISS Wake-Up t MWC t IOENSS Capture OPCODE t CSPID CSCCLK t t SOCDO SOE 3-49 DC and Switching Characteristics LatticeECP2/M Family Data Sheet t DINIT t t HCFG SUCFG Valid Clock 127 Clock 128 7 0 Valid Bitstream XXX ...
Page 102
... Over Recommended Operating Conditions Parameter t t BTS BTH t BTCPL t t BTCOEN BTCRH t BTCRS Data Captured t BTUPOEN 3-50 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min Max — — 20 — 20 — 8 — 10 — 50 — — 10 — 10 — — 25 — — 25 — 25 — ...
Page 103
... Includes Test Fixture and Probe Capacitance 1M 1M 100 100 3-51 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Test Poi nt C Timing Ref. L LVCMOS 3.3 = 1.5V LVCMOS 2 CCIO 0pF LVCMOS 1 CCIO LVCMOS 1 CCIO LVCMOS 1 ...
Page 104
... C]_FB_A PCLK[T, C]_[n:0]_[3:0] © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 105
... Termination resistor switching power (3.3V). This pin must be tied to 3.3V — even if the quad is unused. I Negative Reference Clock Input I Positive Reference Clock Input PLL and Reference clock buffer power (1.2V). This pin must be tied to 1.2V — even if the quad is unused. 4-2 Pinout Information LatticeECP2/M Family Data Sheet Description ...
Page 106
... These signals are relevant for LatticeECP2M family defines the associated channel in the Quad. 3. These signals are defined in Quads [LOC] indicates the corner SERDES Quad is located: ULC (upper left), URC (upper right), LLC (lower left), LRC (lower right). 4. When placing switching I/Os around these critical pins that are designed to supply the device with the proper reference or supply voltage, care must be given ...
Page 107
... In some packages, all the potential DDR data (DQ) pins may not be available. PIC numbering definitions are provided in the “Signal Names” column of the Signal Descriptions table. LatticeECP2/M Family Data Sheet DDR Strobe (DQS) and PIO Within PIC ...
Page 108
... Lattice Semiconductor LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Configuration Muxed Pins Dedicated Pins (Non TAP) Muxed Pins Non Configuration Dedicated Pins VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 Bank3 ...
Page 109
... Lattice Semiconductor LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12 (Cont.) Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces per I/O Bank4 1 Bank Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + Bank VREF1) ...
Page 110
... Lattice Semiconductor LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Configuration Muxed Pins Dedicated Pins (Non TAP) Muxed Pins Non Configuration Dedicated Pins VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 Bank3 ...
Page 111
... Lattice Semiconductor LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35 (Cont.) Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces per I/O Bank4 1 Bank Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + Bank VREF1) ...
Page 112
... Lattice Semiconductor LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Configuration Muxed Pins Dedicated Pins (Non TAP) Muxed Pins Non Configuration Dedicated Pins VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 Bank3 ...
Page 113
... Lattice Semiconductor LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 (Cont.) Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces per I/O Bank4 1 Bank Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + Bank VREF1) ...
Page 114
... Lattice Semiconductor LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Configuration Muxed Pins Dedicated Pins (Non TAP) Muxed Pins Non Configuration Dedicated Pins VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 Bank3 ...
Page 115
... Lattice Semiconductor LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35 (Cont.) Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces per Bank4 1 I/O Bank Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + Bank VREF1) ...
Page 116
... Lattice Semiconductor LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70 and LFE2M100 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Muxed Pins Configuration Dedicated Pins (Non TAP) Muxed Pins Non Configuration Dedicated Pins VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 ...
Page 117
... Lattice Semiconductor LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70 and LFE2M100 (Cont.) Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces Bank4 1 per I/O Bank Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 1 ...
Page 118
... Lattice Semiconductor Available Device Resources by Package, LatticeECP2 Resource Device ECP2-6 ECP2-12 ECP2-20 PLL/DLL ECP2-35 ECP2-50 ECP2-70 Available Device Resources by Package, LatticeECP2M Resource Device ECP2M20 ECP2M35 PLL/DLL ECP2M50 ECP2M70 ECP2M100 256 fpBGA 484 fpBGA 4 — — 4 — 6 — — 256 fpBGA 484 fpBGA ...
Page 119
... Lattice Semiconductor LatticeECP2 Power Supply and NC 3 Signals 144 TQFP VCC 16, 22, 29, 48, 54, 83, 94, 102, 128, 135 VCCIO0 139 VCCIO1 117 VCCIO2 106 VCCIO3 89 VCCIO4 64 VCCIO5 42 VCCIO6 31 VCCIO7 9 VCCIO8 85 VCCJ 35 VCCAUX 6, 39, 90, 142 VCCPLL None 1 GND 11, 21, 30, 47, 51, 61, 81, 95, 105, 120, 133, ...
Page 120
... Lattice Semiconductor LatticeECP2 Power Supply and NC (Cont.) Signals VCC LFE2-20: R8, P18, M8, L20, L12, L13, L14, L15, M11, M12, M15, M16, N11, N16, P11, P16, R11, R12, R15, R16, T12, T13, T14, T15 LFE2-35/LFE2-50: L12, L13, L14, L15, M11, M12, M15, M16, N11, N16, P11, P16, R11, R12, R15, ...
Page 121
... Lattice Semiconductor LatticeECP2M Power Supply and NC Signal V G7, G9, H7, J10, K10 CCIO0 V E10 CCIO1 V E14, G12 CCIO2 V K12, M14 CCIO3 V M10, P12 CCIO4 V M7, P5 CCIO5 V K5, M3 CCIO6 V E3, G5 CCIO7 V T15 CCIO8 V K7 CCJ V G8, H10, J7, K9 CCAUX V G10 CCPLL 3 SERDES Power ...
Page 122
... Lattice Semiconductor LatticeECP2M Power Supply and NC (Cont.) Signal V LFE2M35: AD13, AD14, AD16, AD17, AD19, AD21, CC AD22, AD24, AD25, L12, L13, L14, L15, M11, M12, M15, M16, N11, N16, P11, P16, R11, R12, R15, R16, T12, T13, T14, T15 LFE2M50: L12, L13, L14, L15, M11, M12, M15, M16, ...
Page 123
... Lattice Semiconductor LatticeECP2M Power Supply and NC (Cont.) Signal 1 GND A13, A19, A2, A25, AA2, AA25, AB18, AB22, AB5, AB9, AE1, AE11, AE16, AE22, AE26, AE6, AF13, AF19, AF2, AF25, B1, B11, B16, B22, B26, B6, E18, E22, E5, E9, F2, F25, G11, G16, J22, J5, K11, K13, ...
Page 124
... Lattice Semiconductor LatticeECP2M Power Supply and NC (Cont.) Signal V AA13, AA14, AA15, AA16, AA17, AA18, AA19, AA20, AA21, AA22, AB14, AB15, AB20, AB21, N14, N15, N20, N21, CC P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, R13, R14, R21, R22, T14, T21, U14, U21, V14, V21, W14, W21, ...
Page 125
... PCLKT6_0 T (LVDS)* PCLKC6_0 C (LVDS)* VREF2_6 T VREF1_6 LLM0_PLLCAP T (LVDS)* C (LVDS)* VREF2_5/BDQ6 T VREF1_5/BDQ6 C BDQ6 T BDQ6 C BDQS6 T BDQ6 C 4-22 Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/12SE Pin/Pad Dual Function Bank Function PL2A 7 VREF2_7 PL2B 7 VREF1_7 PL4A 7 PL4B 7 PL6A 7 LDQ10 VCCAUX - PL6B 7 LDQ10 PL8A 7 LDQ10 ...
Page 126
... BDQS24 T BDQ24 C BDQ24 T BDQ24 C VREF2_4/BDQ24 T VREF1_4/BDQ24 C PROGRAMN D0/SPIFASTN D6 D7/SPID0 C VCCIO8 DI/CSSPI0N T DOUT/CSON C BUSY/SISPI T VCCIO3 VCCAUX 4-23 Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/12SE Dual Bank Function PB16B 5 BDQ15 GND - VCC - PB26A 5 PCLKT5_0/BDQ24 PB26B 5 PCLKC5_0/BDQ24 GND - PB31A 4 PCLKT4_0/BDQ33 PB31B 4 PCLKC4_0/BDQ33 VCC - PB34A ...
Page 127
... C PCLKT2_0/RDQ10 T VREF2_2 C (LVDS)* VREF1_2 T (LVDS)* VREF2_1 C VREF1_1 PCLKC1_0 C PCLKT1_0 T PCLKC0_0 C PCLKT0_0 T 4-24 Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/12SE Pin/Pad Dual Function Bank Function PR20B 3 RLM0_GPLLC_IN_A** PR20A 3 RLM0_GPLLT_IN_A** 3 VCC - GND - PR17B 3 RLM0_GDLLC_IN_A** PR17A 3 RLM0_GDLLT_IN_A** PR16B 3 VREF2_3 PR16A 3 VREF1_3 PR15B 3 PCLKC3_0 PR15A ...
Page 128
... GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one-to-one connection with a package ball or pin. Pin/Pad Dual Function Differential Function C T VCCIO0 C T VCCAUX VREF2_0 C VREF1_0 T 4-25 Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/12SE Dual Bank Function PT16B 0 PT16A 0 GND - 0 PT6B 0 PT6A 0 - PT2B ...
Page 129
... C PL31B PL33A LDQ28 T (LVDS)* PL38A VCCIO6 LDQ28 C (LVDS)* PL38B VCC LDQ28 T (LVDS)* PL40A GND LDQ28 C (LVDS)* PL40B VCCIO6 LDQS28 T (LVDS)* PL42A 4-26 Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE Dual Bank Function Differential 7 VREF2_7 7 VREF1_7 7 LDQ8 7 LDQ8 - 7 LDQ16 - 7 LDQ16 7 LDQ16 7 7 LDQ16 ...
Page 130
... VCC GND BDQ33 T PB42A BDQ33 C PB42B BDQ33 T PB44A BDQ33 C PB44B VCCAUX BDQ42 T PB50A BDQ42 C PB50B GND BDQS42 T PB52A BDQ42 C PB52B 4-27 Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE Dual Bank Function 6 LDQ42 6 LDQ42 - - - - - 5 VREF2_5/BDQ6 5 VREF1_5/BDQ6 5 5 BDQS6 5 BDQ6 5 BDQ6 5 BDQ6 - 5 BDQ15 ...
Page 131
... PR31A VCCAUX C (LVDS)* PR30B T (LVDS)* PR30A RLM0_PLLCAP VCC C PR28B T PR28A C (LVDS)* PR27B T (LVDS)* PR27A C PR22B VCCIO3 T PR22A C (LVDS)* PR21B 4-28 Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE Dual Bank Function Differential 4 BDQ51 4 4 BDQ51 4 BDQ60 4 BDQ60 - 4 BDQS60 4 BDQ60 4 4 BDQ60 - 4 VREF2_4/BDQ60 ...
Page 132
... PT58A C PT56B T PT56A GND VCCIO1 VCC C PT50B T PT50A VCCAUX GND C PT44B T PT44A C PT42B T PT42A C PT39B T PT39A XRES C PT37B 4-29 Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE Dual Bank Function Differential 3 PCLKT3_0/RDQ25 - - 2 PCLKC2_0/RDQ16 2 PCLKT2_0/RDQ16 2 2 RDQS16 - - 2 RDQ16 2 2 RDQ16 2 RDQ16 - 2 RDQ16 2 RDQ8 ...
Page 133
... Function GND T PT37A C PT36B T PT36A VCC C PT30B VCCAUX T PT30A GND C PT26B T PT26A VCCIO0 C PT20B T PT20A VCC C PT12B T PT12A GND C PT8B T PT8A C PT6B T PT6A VCCIO0 C PT2B T PT2A 4-30 Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE Dual Bank Function Differential - 0 PCLKT0_0 VREF2_0 0 VREF1_0 ...
Page 134
... PL16A GNDIO6 VREF1_6 C PL16B T (LVDS)* PL17A C (LVDS)* PL17B T PL18A C PL18B LLM0_PLLCAP T (LVDS)* PL20A GNDIO6 T PL21A C (LVDS)* PL20B VCCIO6 C PL21B 4-31 Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE Bank Dual Function PL2A 7 VREF2_7 PL2B 7 VREF1_7 PL5A 7 PL4A 7 PL5B 7 - PL4B 7 PL7A 7 LDQ10 PL7B ...
Page 135
... PB23A VCCIO5 BDQ6 C PB22B BDQ6 C PB23B GNDIO5 BDQS6 T PB24A BDQ6 T PB25A BDQ6 C PB24B BDQ6 C PB25B T PB26A VCCIO5 4-32 Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE Bank Dual Function Differential - 6 LDQ28 T (LVDS)* 6 LDQ28 6 LDQ28 C (LVDS)* 6 LDQ28 6 6 LDQ28 T (LVDS)* 6 LDQ28 6 LDQ28 C (LVDS)* 6 ...
Page 136
... PB52A BDQ24 C PB51B BDQ24 C PB52B BDQ24 T PB53A BDQ24 T PB54A VCCIO4 BDQ24 C PB53B BDQ24 C PB54B GNDIO4 T PB55A C PB55B CFG2 4-33 Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE Bank Dual Function Differential 5 PCLKC5_0/BDQ24 - 4 PCLKT4_0/BDQ33 4 PCLKC4_0/BDQ33 4 4 BDQ33 4 BDQ33 4 BDQS33 - 4 BDQ33 4 BDQ33 4 BDQ33 4 BDQ33 ...
Page 137
... PR17B GNDIO3 T (LVDS)* PR17A VREF2_3 C PR16B VCCIO3 VREF1_3 T PR16A PCLKC3_0 C (LVDS)* PR15B PCLKT3_0 T (LVDS)* PR15A C PR13B GNDIO2 T PR13A 4-34 Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE Bank Dual Function CFG1 8 8 CFG0 8 8 WRITEN INITN 8 8 CSN - CCLK 8 8 CS1N DONE ...
Page 138
... PT53A C PT52B C PT51B T PT52A T PT51A C PT50B GNDIO1 C PT49B T PT50A VCCIO1 T PT49A C PT48B C PT47B T PT48A T PT47A 4-35 Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE Bank Dual Function Differential 2 RDQ10 2 RDQ10 C (LVDS)* 2 RDQ10 2 2 RDQ10 T (LVDS)* 2 RDQ10 C (LVDS)* 2 RDQS10 T (LVDS RDQ10 C (LVDS)* 2 RDQ10 2 ...
Page 139
... PCLKC0_0 C PT28B GNDIO0 PCLKT0_0 T PT28A C PT27B C PT26B T PT27A VCCIO0 T PT26A C PT25B C PT24B T PT25A T PT24A C PT23B GNDIO0 C PT22B T PT23A VCCIO0 T PT22A C PT21B T PT21A GNDIO0 VCCIO 4-36 Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE Bank Dual Function Differential PCLKC1_0 1 PCLKT1_0 1 0 PCLKC0_0 - 0 PCLKT0_0 ...
Page 140
... VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO8 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 4-37 Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE Bank Dual Function Differential 0 VREF2_0 0 VREF1_0 - - - - - - - - - - ...
Page 141
... Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. LatticeECP2/M Family Data Sheet LFE2-12E/SE Ball/Pad ...
Page 142
... GNDIO6 - PL22B 6 PL27A 6 PL27B 6 VCC - PL28A 6 PL28B 6 LLM0_PLLCAP 6 PL30A 6 GNDIO6 - 4-39 Pinout Information LatticeECP2/M Family Data Sheet Dual Function Differential VREF2_7 T (LVDS)* VREF1_7 C (LVDS)* LDQ8 LDQ8 T (LVDS)* LDQ8 LDQ8 C (LVDS)* LDQ16 LDQ16 LDQ16 LDQ16 T (LVDS)* LDQ16 LDQ16 C (LVDS)* LDQS16 T (LVDS)* LDQ16 ...
Page 143
... PB5B 5 VCCIO 5 GNDIO5 5 PB30A 5 PB30B 5 PB31A 5 PB32A 5 VCCIO5 5 PB31B 5 PB32B 5 4-40 Pinout Information LatticeECP2/M Family Data Sheet Dual Function Differential LLM0_GPLLT_FB_A/LDQ34 LLM0_GPLLC_IN_A**/LDQ34 C (LVDS)* LLM0_GPLLC_FB_A/LDQ34 LDQ42 T (LVDS)* LDQ42 LDQ42 C (LVDS)* LDQ42 LDQ42 T (LVDS)* LDQ42 LDQ42 C (LVDS)* LDQ42 LDQ42 LDQS42 T (LVDS)* LDQ42 ...
Page 144
... PB57B 4 PB58A 4 PB59A 4 VCCIO4 4 PB58B 4 PB59B 4 PB60A 4 GNDIO4 - PB61A 4 PB60B 4 4-41 Pinout Information LatticeECP2/M Family Data Sheet Dual Function Differential BDQS33 BDQ33 BDQ33 BDQ33 PCLKT5_0/BDQ33 PCLKC5_0/BDQ33 PCLKT4_0/BDQ42 PCLKC4_0/BDQ42 BDQ42 BDQ42 BDQS42 BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 BDQ60 ...
Page 145
... VCCIO8 8 PR39A 8 PR38B 8 PR38A 8 GNDIO8 - PR31B 3 VCCIO3 3 PR31A 3 GNDIO3 - PR30B 3 PR30A 3 RLM0_PLLCAP 3 4-42 Pinout Information LatticeECP2/M Family Data Sheet Dual Function Differential BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 VREF2_4/BDQ60 VREF1_4/BDQ60 WRITEN CSN CS1N D1 D0/SPIFASTN D7/SPID0 D5 DI/CSSPI0N DOUT/CSON BUSY/SISPI RLM0_GPLLC_FB_A/RDQ34 RLM0_GPLLT_FB_A/RDQ34 RLM0_GPLLC_IN_A**/RDQ34 ...
Page 146
... PR7A 2 PR2B 2 VCCIO2 2 PR2A 2 PT64B 1 PT64A 1 GNDIO1 - PT63B 1 PT62B 1 PT63A 1 4-43 Pinout Information LatticeECP2/M Family Data Sheet Dual Function Differential RLM0_GDLLC_FB_A/RDQ25 RLM0_GDLLT_FB_A/RDQ25 RLM0_GDLLC_IN_A**/RDQ25 C (LVDS)* RLM0_GDLLT_IN_A**/RDQ25 T (LVDS)* VREF2_3/RDQ25 VREF1_3/RDQ25 PCLKC3_0/RDQ25 C (LVDS)* PCLKT3_0/RDQ25 T (LVDS)* PCLKC2_0/RDQ16 PCLKT2_0/RDQ16 RDQ16 RDQ16 C (LVDS)* RDQ16 RDQ16 ...
Page 147
... PT56A 1 GNDIO1 1 VCCIO 1 PT46B 1 PT46A 1 GNDIO1 - PT45B 1 PT44B 1 PT45A 1 PT44A 1 VCCIO1 1 PT43B 1 PT42B 1 PT43A 1 PT42A 1 GNDIO1 - PT41B 1 PT40B 1 PT41A 1 PT40A 1 VCCIO1 1 PT39B 1 PT39A 1 XRES 1 PT37B 0 GNDIO0 - PT37A 0 4-44 Pinout Information LatticeECP2/M Family Data Sheet Dual Function Differential PCLKC1_0 PCLKT1_0 PCLKC0_0 PCLKT0_0 ...
Page 148
... VCCIO0 0 PT31A 0 PT30B 0 PT30A 0 GNDIO0 0 VCCIO 0 PT2B 0 PT2A 0 VCC - VCC - VCC - VCC - VCC - VCC - VCCAUX - VCCAUX - VCCAUX - VCCAUX - VCCIO0 0 VCCIO0 0 VCCIO1 1 VCCIO1 1 VCCIO2 2 VCCIO2 2 VCCIO3 3 VCCIO3 3 VCCIO4 4 VCCIO4 4 VCCIO5 5 4-45 Pinout Information LatticeECP2/M Family Data Sheet Dual Function Differential VREF2_0 VREF1_0 ...
Page 149
... LFE2-20E/SE Ball/Pad Function Bank VCCIO5 5 VCCIO6 6 VCCIO6 6 VCCIO7 7 VCCIO7 7 VCCIO8 8 GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - 4-46 Pinout Information LatticeECP2/M Family Data Sheet Dual Function Differential ...
Page 150
... T PL17A VCCIO7 LDQ10 C PL17B LDQ10 T (LVDS)* PL18A GNDIO LDQ10 C (LVDS)* PL18B T PL19A C PL19B PCLKT6_0 T (LVDS)* PL21A PCLKC6_0 C (LVDS)* PL21B 4-47 Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/20SE Bank Dual Function 7 VREF2_7 7 VREF1_7 - 7 LDQ8 7 LDQ8 7 LDQ8 7 LDQ8 7 7 LDQ8 7 LDQ8 7 LDQ8 7 LDQ8 ...
Page 151
... PL38A LDQ28 T PL41A VCCIO6 LDQ28 C (LVDS)* PL38B LDQ28 C PL41B LDQ28 T (LVDS)* PL40A LDQ28 T PL43A GNDIO LDQ28 C PL43B LDQ28 C (LVDS)* PL40B 4-48 Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/20SE Bank Dual Function 6 VREF2_6/LDQ25 - 6 VREF1_6/LDQ25 6 6 LDQ25 6 LDQ25 6 LDQ25 6 LDQ25 - 6 LDQS25 6 LDQ25 6 LDQ25 6 ...
Page 152
... T PB21A BDQ15 T PB20A BDQ15 C PB21B BDQ15 C PB20B BDQ15 T PB23A VCCIO5 BDQ15 T PB22A BDQ15 C PB23B BDQ15 C PB22B BDQ15 T PB25A GNDIO 4-49 Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/20SE Bank Dual Function 6 LDQ42 6 6 LDQS42 6 LDQ42 6 LDQ42 6 LDQ42 - 6 LDQ42 - - - - - 5 BDQ6 5 VREF2_5/BDQ6 5 BDQ6 5 VREF1_5/BDQ6 ...
Page 153
... BDQ33 C PB43B BDQ33 C PB42B BDQ33 T PB45A VCCIO4 BDQ33 T PB44A BDQ33 C PB45B BDQ33 C PB44B BDQ33 T PB46A GNDIO4 BDQ33 C PB46B 4-50 Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/20SE Bank Dual Function 5 BDQS24 5 BDQ24 5 BDQ24 5 BDQ24 5 5 BDQ24 5 BDQ24 5 BDQ24 - 5 BDQ33 5 BDQ33 5 BDQ33 5 BDQ33 ...
Page 154
... BDQ51 T PB61A VCCIO4 BDQ51 T PB63A BDQ51 C PB61B BDQ51 C PB63B GNDIO4 T PB64A C PB64B CFG2 CFG1 PROGRAMN CFG0 D1 C PR42B 4-51 Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/20SE Bank Dual Function 4 BDQ51 4 BDQ51 4 BDQ51 4 BDQ51 4 4 BDQ51 4 BDQ51 - 4 BDQ51 4 BDQS51 4 BDQ51 4 BDQ51 4 BDQ51 ...
Page 155
... VCCIO3 C PR31B T PR31A C (LVDS)* PR30B T (LVDS)* PR30A RLM0_PLLCAP C PR28B C (LVDS)* PR27B GNDIO3 T PR28A T (LVDS)* PR27A PR26B VCCIO3 PR26A PR23B GNDIO PR24B PR23A PR24A 4-52 Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/20SE Bank Dual Function 8 8 WRITEN - 8 8 CS1N CSN D0/SPIFASTN D7/SPID0 8 ...
Page 156
... GNDIO PR10A PR11A PR8B PR9B VCCIO2 PR8A PR9A C PR7B GNDIO2 C (LVDS)* PR6B T PR7A T (LVDS)* PR6A C PR5B VCCIO2 PR4B T PR5A PR4A 4-53 Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/20SE Bank Dual Function 3 VREF2_3/RDQ25 3 3 VREF1_3/RDQ25 3 PCLKC3_0/RDQ25 3 PCLKT3_0/RDQ25 2 PCLKC2_0/RDQ16 - 2 PCLKT2_0/RDQ16 2 RDQ16 2 RDQ16 2 RDQ16 2 2 ...
Page 157
... PT59A VCCIO1 C PT56B C PT57B T PT56A T PT57A C PT55B GNDIO1 T PT55A C PT53B C PT54B T PT53A VCCIO1 T PT54A C PT51B C PT52B T PT51A T PT52A C PT49B GNDIO1 T PT49A VCCIO1 T PT48A C PT48B C PT46B C PT45B 4-54 Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/20SE Bank Dual Function - 2 VREF2_2 2 VREF1_2 1 VREF2_1 1 VREF1_1 - ...
Page 158
... PT20A 0 A6 PT21A 0 GNDIO GNDIO0 - C7 PT17B 0 D10 PT18B 0 C6 PT17A 0 E10 PT18A 0 VCCIO VCCIO0 0 F10 PT15B 0 B6 PT16B 0 LatticeECP2/M Family Data Sheet LFE2-20E/20SE Ball/Pad Differential Function Bank GNDIO1 - T PT46A 1 T PT45A 1 C PT44B 1 C PT43B 1 VCCIO1 1 T PT44A 1 T PT43A 1 C PT42B ...
Page 159
... PT9A VCCIO0 C PT6B C PT7B T PT6A T PT7A GNDIO C PT4B C PT5B T PT4A T PT5A VCCIO0 VREF2_0 C PT2B C PT3B VREF1_0 T PT2A T PT3A VCC VCC VCC VCC VCC VCC VCC VCC VCC 4-56 Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/20SE Bank Dual Function VREF2_0 0 0 VREF1_0 ...
Page 160
... J8 VCCIO7 7 K7 VCCIO7 7 L7 VCCIO7 7 M7 VCCIO7 7 P15 VCCIO8 8 R15 VCCIO8 8 C5 VCCAUX - D11 VCCAUX - E17 VCCAUX - E6 VCCAUX - LatticeECP2/M Family Data Sheet LFE2-20E/20SE Ball/Pad Differential Function Bank VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCCIO0 0 VCCIO0 0 VCCIO0 0 VCCIO0 0 VCCIO1 1 VCCIO1 ...
Page 161
... K11 GND - K12 GND - K13 GND - K15 GND - K8 GND - L10 GND - L11 GND - L12 GND - L13 GND - L15 GND - LatticeECP2/M Family Data Sheet LFE2-20E/20SE Ball/Pad Differential Function Bank VCCAUX - VCCAUX - VCCAUX - VCCAUX - VCCAUX - VCCAUX - VCCAUX - VCCAUX - VCCAUX - VCCAUX - VCCAUX - VCCAUX - GND ...
Page 162
... Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. LatticeECP2/M Family Data Sheet LFE2-20E/20SE Ball/Pad ...
Page 163
... LDQ22 T PL40A LDQ22 C PL40B GNDIO7 LDQS22 T (LVDS)* PL41A LDQ22 C (LVDS)* PL41B LDQ22 T PL42A VCCIO LDQ22 C PL42B LDQ22 T (LVDS)* PL43A 4-60 Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE Bank Dual Function 7 VREF2_7 7 VREF1_7 - 7 7 LDQ16 7 LDQ16 7 LDQ16 7 LDQ16 7 LDQ16 7 7 LDQ16 7 LDQ16 ...
Page 164
... LDQ56 C (LVDS)* PL71B LDQ56 T PL72A LDQ56 C PL72B VCCIO LDQ56 T (LVDS)* PL73A LDQ56 C (LVDS)* PL73B LDQ56 T PL74A LDQ56 C PL74B GNDIO6 4-61 Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE Bank Dual Function 7 LDQ41 7 PCLKT7_0/LDQ41 - 7 PCLKC7_0/LDQ41 6 PCLKT6_0/LDQ50 6 PCLKC6_0/LDQ50 6 VREF2_6/LDQ50 6 VREF1_6/LDQ50 6 LDQ50 6 6 LDQ50 6 LDQ50 ...
Page 165
... T PB29A BDQ24 C PB29B BDQ24 T PB30A BDQ24 C PB30B BDQ24 T PB31A VCCIO BDQ24 C PB31B BDQ24 T PB32A BDQ24 C PB32B BDQS24 T PB33A GNDIO5 4-62 Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE Bank Dual Function 6 LDQS75 6 LDQ75 6 LDQ75 6 6 LDQ75 6 LDQ75 6 LDQ75 6 LDQ75 - 6 LDQ75 - - - - - 5 VREF2_5/BDQ6 5 VREF1_5/BDQ6 ...
Page 166
... BDQ42 T PB53A VCCIO BDQ42 C PB53B BDQ42 T PB54A BDQ42 C PB54B BDQ42 T PB55A GNDIO4 BDQ42 C PB55B BDQ51 T PB57A BDQ51 C PB57B 4-63 Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE Bank Dual Function 5 BDQ33 5 BDQ33 5 BDQ33 5 BDQ33 5 5 BDQ33 5 BDQ33 5 BDQ33 - 5 BDQ42 5 BDQ42 5 BDQ42 5 BDQ42 ...
Page 167
... PB80A BDQ69 C PB80B VCCIO BDQ69 T PB81A BDQ69 C PB81B T PB82A C PB82B GNDIO4 CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GNDIO8 4-64 Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE Bank Dual Function 4 BDQ60 4 BDQ60 4 4 BDQ60 4 BDQ60 - 4 BDQS60 4 BDQ60 4 BDQ60 4 BDQ60 4 BDQ60 4 BDQ60 ...
Page 168
... RDQ39 C PR59B RDQ39 T PR59A VCCIO GNDIO3 RDQ31 C PR49B RDQ31 T PR49A RDQ31 C (LVDS)* PR48B RDQ31 T (LVDS)* PR48A VCCIO C PR47B T PR47A C (LVDS)* PR46B T (LVDS)* PR46A 4-65 Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE Bank Dual Function 8 WRITEN 8 CS1N 8 CSN 8 D0/SPIFASTN D7/SPID0 8 8 DI/CSSPI0N ...
Page 169
... PR16A GNDIO2 RDQ14 C PR15B RDQ14 T PR15A RDQ14 C (LVDS)* PR14B RDQ14 T (LVDS)* PR14A VCCIO RDQ14 C PR13B RDQ14 T PR13A RDQ14 C (LVDS)* PR12B 4-66 Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE Bank Dual Function 2 PCLKC2_0/RDQ41 2 PCLKT2_0/RDQ41 - 2 RDQ41 2 RDQ41 2 RDQ41 2 RDQ41 2 2 RDQ41 2 RDQS41 2 RDQ41 - 2 ...
Page 170
... PT76A C PT75B T PT75A C PT74B T PT74A GNDIO1 VCCIO C PT64B GNDIO1 T PT64A C PT63B T PT63A C PT62B VCCIO T PT62A C PT61B T PT61A C PT60B T PT60A GNDIO1 C PT58B VCCIO T PT58A C PT57B T PT57A 4-67 Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE Bank Dual Function 2 RDQ16 VREF2_2 2 VREF1_2 1 VREF2_1 - 1 VREF1_1 ...
Page 171
... PT45A C PT44B VCCIO T PT44A C PT43B T PT43A C PT42B T PT42A C PT41B GNDIO0 T PT41A VCCIO C PT39B T PT39A C PT38B T PT38A GNDIO0 C PT36B T PT36A C PT35B T PT35A VCCIO C PT34B T PT34A 4-68 Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE Bank Dual Function PCLKC1_0 1 PCLKT1_0 1 0 PCLKC0_0 0 0 PCLKT0_0 ...
Page 172
... PT8A C PT7B T PT7A C PT6B T PT6A GNDIO0 C PT5B T PT5A C PT4B VCCIO T PT4A C PT3B T PT3A VREF2_0 C PT2B VREF1_0 T PT2A VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 4-69 Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE Bank Dual Function VREF2_0 0 VREF1_0 ...
Page 173
... R14 VCCIO4 4 T12 VCCIO4 4 T13 VCCIO4 4 T14 VCCIO4 4 R9 VCCIO5 5 T10 VCCIO5 5 T11 VCCIO5 5 T9 VCCIO5 5 N7 VCCIO6 6 P7 VCCIO6 6 LatticeECP2/M Family Data Sheet LFE2-50E/SE Ball/Pad Differential Function Bank VCC - VCC - VCC - VCC - VCC - VCCAUX 0 VCCAUX 0 VCCAUX 1 VCCAUX 1 VCCAUX 2 VCCAUX 2 VCCAUX 3 ...
Page 174
... GND - M12 GND - M13 GND - M15 GND - M8 GND - Ball/Pad Dual Function Differential Function VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 4-71 Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE Bank Dual Function GND - GND - GND - GND - GND - GND - GND - GND - GND ...
Page 175
... GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. Ball/Pad Dual Function Differential Function VCCPLL VCCPLL VCCPLL VCCPLL 4-72 Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE Bank Dual Function GND - GND - GND - GND - ...
Page 176
... PL15A LDQ8 C PL15B VCCIO7 LDQ8 T (LVDS)* PL16A LDQ8 C (LVDS)* PL16B LDQ8 T PL17A LDQ8 C PL17B GNDIO7 VCCIO7 NC NC GNDIO7 NC NC 4-73 Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/35SE Bank Dual Function 7 VREF2_7/LDQ6 7 VREF1_7/LDQ6 - 7 LDQ6 7 LDQ6 7 7 LDQ6 7 LDQ6 7 LDQ6 7 LDQ6 - 7 LDQS6 7 LDQ6 ...
Page 177
... LDQ16 C (LVDS)* LDQ16 T VCCIO7 LDQ16 C LDQ16 T (LVDS)* LDQ16 C (LVDS)* T GNDIO7 C T (LVDS)* C (LVDS LDQ25 T (LVDS)* VCCIO6 LDQ25 C (LVDS)* LDQ25 T LDQ25 C GNDIO6 VCCIO6 4-74 Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/35SE Bank Dual Function PL18A 7 LDQ22 PL19A 7 LDQ22 PL19B 7 LDQ22 7 PL20A 7 LDQ22 ...
Page 178
... LDQ34 T (LVDS)* PL50A LDQ34 C (LVDS)* PL50B LDQ34 T PL51A LDQ34 C PL51B GNDIO6 LDQ42 T (LVDS)* PL52A LDQ42 C (LVDS)* PL52B LDQ42 T PL53A LDQ42 C PL53B 4-75 Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/35SE Bank Dual Function - - - - - LDQ39 6 LDQ39 - 6 LDQS39*** 6 LDQ39 6 LDQ39 6 6 LDQ39 6 LLM0_GDLLT_IN_A**/LDQ39 ...
Page 179
... PB8B VCCIO5 BDQ6 T PB9A BDQ6 C PB9B BDQ6 T PB10A BDQ6 C PB10B VCCIO5 GNDIO5 BDQ15 T PB11A BDQ15 C PB11B BDQ15 T PB12A 4-76 Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/35SE Bank Dual Function 6 6 LDQ56 6 LDQ56 6 LDQ56 6 LDQ56 - 6 LDQS56 6 LDQ56 6 LDQ56 6 6 LDQ56 6 LDQ56 6 LDQ56 ...
Page 180
... C BDQ24 T VCCIO5 BDQ24 C BDQ24 T BDQ24 C BDQ24 T GNDIO5 BDQ24 C BDQ33 T BDQ33 C BDQ33 T BDQ33 C BDQ33 T BDQ33 C 4-77 Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/35SE Bank Dual Function PB12B 5 BDQ15 PB13A 5 BDQ15 PB13B 5 BDQ15 5 PB14A 5 BDQ15 PB14B 5 BDQ15 - PB15A 5 BDQS15 PB15B 5 BDQ15 PB16A 5 BDQ15 ...
Page 181
... BDQ51 T PB50A BDQ51 C PB50B GNDIO4 BDQS51 T PB51A BDQ51 C PB51B BDQ51 T PB52A BDQ51 C PB52B BDQ51 T PB53A BDQ51 C PB53B VCCIO4 4-78 Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/35SE Bank Dual Function 5 5 BDQ33 5 BDQ33 - 5 BDQS33 5 BDQ33 5 BDQ33 5 BDQ33 5 PCLKT5_0/BDQ33 5 PCLKC5_0/BDQ33 PCLKT4_0/BDQ42 4 4 PCLKC4_0/BDQ42 ...
Page 182
... BDQ60 C PB69B BDQ60 T PB70A BDQ60 C PB70B BDQ60 T PB71A BDQ60 C PB71B VCCIO4 BDQ60 T PB72A BDQ60 C PB72B T PB73A C PB73B GNDIO4 CFG2 CFG1 CFG0 PROGRAMN 4-79 Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/35SE Bank Dual Function 4 BDQ51 4 BDQ51 4 BDQ51 4 BDQ51 - 4 BDQ60 4 BDQ60 4 BDQ60 4 BDQ60 - ...
Page 183
... GNDIO3 RDQ34 C PR47B RDQ34 T PR47A RDQ34 C (LVDS)* PR46B RDQ34 T (LVDS)* PR46A VCCIO3 C PR45B T PR45A C (LVDS)* PR44B T (LVDS)* PR44A RLM0_PLLCAP VCCPLL C PR42B T PR42A GNDIO3 C (LVDS)* PR41B 4-80 Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/35SE Bank Dual Function WRITEN 8 CS1N 8 CSN 8 D0/SPIFASTN D7/SPID0 8 ...
Page 184
... GNDIO2 RDQ16 C (LVDS)* PR24B RDQ16 T (LVDS)* PR24A RDQ16 C PR23B RDQ16 T PR23A VCCIO2 RDQ16 C (LVDS)* PR22B RDQS16 T (LVDS)* PR22A RDQ16 C PR21B 4-81 Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/35SE Bank Dual Function 3 RLM0_GDLLT_IN_A**/RDQ39 3 RDQ39 3 RDQ39 3 3 RDQ39 3 RDQS39*** 3 RDQ39 - 3 RDQ39 - - - ...
Page 185
... RDQ8 T PR13A RDQ8 C (LVDS)* PR12B RDQ8 T (LVDS)* PR12A VCCIO2 RDQ8 C PR11B RDQ8 T PR11A RDQ8 C (LVDS)* PR10B RDQ8 T (LVDS)* PR10A PR9B PR9A GNDIO2 4-82 Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/35SE Bank Dual Function - 2 RDQ22 2 RDQ22 2 RDQ22 2 RDQ22 2 2 RDQ22 2 RDQ22 2 RDQ22 - ...
Page 186
... PT70A C PT69B T PT69A C PT68B GNDIO1 T PT68A C PT67B VCCIO1 T PT67A C PT66B T PT66A C PT65B T PT65A GNDIO1 NC NC VCCIO1 4-83 Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/35SE Bank Dual Function 2 RDQ6 2 RDQ6 2 RDQ6 2 RDQ6 2 2 RDQ6 2 RDQS6 2 RDQ6 - 2 RDQ6 2 RDQ6 2 RDQ6 2 RDQ6 2 2 RDQ6 - ...
Page 187
... PT46A 1 GND GNDIO1 - C15 PT45B 1 A15 PT45A 1 A13 PT44B 1 B13 PT44A 1 VCCIO VCCIO1 1 H17 PT43B 1 H15 PT43A 1 D13 PT42B 1 C14 PT42A 1 GND GNDIO1 - G14 PT41B 1 LatticeECP2/M Family Data Sheet LFE2-35E/35SE Ball/Pad Differential Function Bank NC - GNDIO1 - VCCIO1 PT55B 1 GNDIO1 - T PT55A 1 C PT54B ...
Page 188
... PT31B VCCIO0 T PT31A C PT30B T PT30A C PT29B T PT29A C PT28B T PT28A GNDIO0 C PT27B T PT27A C PT26B T PT26A VCCIO0 C PT25B T PT25A C PT24B T PT24A GNDIO0 C PT23B T PT23A C PT22B T PT22A VCCIO0 4-85 Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/35SE Bank Dual Function PCLKC1_0 1 PCLKT1_0 1 0 PCLKC0_0 - 0 PCLKT0_0 ...
Page 189
... PT13B VCCIO0 GNDIO0 VCCIO0 GNDIO0 VCCIO0 C PT10B GNDIO0 T PT10A C PT9B T PT9A C PT8B VCCIO0 T PT8A C PT7B T PT7A C PT6B T PT6A C PT5B GNDIO0 T PT5A C PT4B VCCIO0 T PT4A C PT3B T PT3A VREF2_0 C PT2B VREF1_0 T PT2A 4-86 Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/35SE Bank Dual Function ...
Page 190
... R18 VCCIO3 3 T23 VCCIO3 3 V20 VCCIO3 3 AC16 VCCIO4 4 AC21 VCCIO4 4 U15 VCCIO4 4 V15 VCCIO4 4 Y18 VCCIO4 4 AC11 VCCIO5 5 AC6 VCCIO5 5 LatticeECP2/M Family Data Sheet LFE2-35E/35SE Ball/Pad Differential Function Bank VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - ...
Page 191
... AD11 GND - AD16 GND - AD21 GND - AD6 GND - AE1 GND - AE26 GND - AF2 GND - AF25 GND - B1 GND - B26 GND - LatticeECP2/M Family Data Sheet LFE2-35E/35SE Ball/Pad Differential Function Bank VCCIO5 5 VCCIO5 5 VCCIO5 5 VCCIO6 6 VCCIO6 6 VCCIO6 6 VCCIO6 6 VCCIO6 6 VCCIO7 7 VCCIO7 7 VCCIO7 7 VCCIO7 7 VCCIO7 ...
Page 192
... P17 GND - R13 GND - R14 GND - T10 GND - T11 GND - T16 GND - T17 GND - T24 GND - T3 GND - U10 GND - LatticeECP2/M Family Data Sheet LFE2-35E/35SE Ball/Pad Differential Function Bank GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND ...
Page 193
... Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. LatticeECP2/M Family Data Sheet LFE2-35E/35SE Ball/Pad ...
Page 194
... LDQ16 C (LVDS)* PL31B LDQ16 T PL32A LDQ16 C PL32B GNDIO7 VCCIO7 LDQ24 T PL36A LDQ24 C PL36B GNDIO7 LDQS24*** T (LVDS)* PL37A LDQ24 C (LVDS)* PL37B 4-91 Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Bank Dual Function 7 VREF2_7 7 VREF1_7 - 7 LDQ21 7 LDQ21 7 7 LDQ21 7 LDQ21 7 LDQ21 7 LDQ21 - 7 LDQS21 7 ...
Page 195
... PL63A GNDIO6 LDQ50 C (LVDS)* PL63B LDQ50 T PL64A LDQ50 C PL64B VCCIO6 LDQ50 T (LVDS)* PL65A LDQ50 C (LVDS)* PL65B LDQ50 T PL66A LDQ50 C PL66B 4-92 Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Bank Dual Function 7 LUM0_SPLLT_IN_A/LDQ37 7 7 LUM0_SPLLC_IN_A/LDQ37 7 LUM0_SPLLT_FB_A/LDQ37 7 LUM0_SPLLC_FB_A/LDQ37 - - LDQ54 7 LDQ54 7 LDQ54 7 7 LDQ54 ...
Page 196
... T (LVDS)* PL82A LDQ67 C (LVDS)* PL82B LDQ67 T PL83A LDQ67 C PL83B GNDIO6 LDQ75 T (LVDS)* PL84A LDQ75 C (LVDS)* PL84B LDQ75 T PL85A LDQ75 C PL85B 4-93 Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Bank Dual Function - 6 LDQ71 6 LDQ71 6 LDQ71 6 LDQ71 6 6 LDQ71 6 LDQ71 6 LDQ71 6 LDQ71 - 6 LDQS71 6 ...
Page 197
... PB8B VCCIO5 BDQ6 T PB9A BDQ6 C PB9B BDQ6 T PB10A BDQ6 C PB10B VCCIO5 GNDIO5 BDQ24 T PB29A BDQ24 C PB29B BDQ24 T PB30A 4-94 Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Bank Dual Function 6 6 LDQ88 6 LDQ88 6 LDQ88 6 LDQ88 - 6 LDQS88 6 LDQ88 6 LDQ88 6 6 LDQ88 6 LDQ88 6 LDQ88 ...
Page 198
... PB45B BDQ33 T PB46A GNDIO5 BDQ33 C PB46B BDQ42 T PB47A BDQ42 C PB47B BDQ42 T PB48A BDQ42 C PB48B BDQ42 T PB49A BDQ42 C PB49B 4-95 Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Bank Dual Function 5 BDQ33 5 BDQ33 5 BDQ33 5 5 BDQ33 5 BDQ33 - 5 BDQS33 5 BDQ33 5 BDQ33 5 BDQ33 5 BDQ33 5 BDQ33 ...
Page 199
... BDQ60 T PB68A BDQ60 C PB68B GNDIO4 BDQS60 T PB69A BDQ60 C PB69B BDQ60 T PB70A BDQ60 C PB70B BDQ60 T PB71A BDQ60 C PB71B VCCIO4 4-96 Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Bank Dual Function 5 5 BDQ51 5 BDQ51 - 5 BDQS51 5 BDQ51 5 BDQ51 5 BDQ51 5 PCLKT5_0/BDQ51 5 PCLKC5_0/BDQ51 PCLKT4_0/BDQ60 4 4 PCLKC4_0/BDQ60 ...
Page 200
... BDQ78 C PB97B BDQ78 T PB98A BDQ78 C PB98B VCCIO4 BDQ78 T PB99A BDQ78 C PB99B T PB100A C PB100B GNDIO4 CFG2 CFG1 CFG0 PROGRAMN 4-97 Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Bank Dual Function 4 BDQ69 4 BDQ69 4 BDQ69 4 BDQ69 - 4 BDQ78 4 BDQ78 4 BDQ78 4 BDQ78 4 BDQ78 4 4 BDQ78 4 BDQ78 ...