LFXP2-8E-5TN144I | |
|---|---|
| Manufacturer Part Number | LFXP2-8E-5TN144I |
| Description | FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd |
| Manufacturer | Lattice |
| LFXP2-8E-5TN144I datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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Specifications of LFXP2-8E-5TN144I | |||
|---|---|---|---|
| Number Of Macrocells | 8000 | Number Of Programmable I/os | 100 |
| Data Ram Size | 226304 | Supply Voltage (max) | 1.26 V |
| Maximum Operating Temperature | + 100 C | Minimum Operating Temperature | - 40 C |
| Mounting Style | SMD/SMT | Supply Voltage (min) | 1.14 V |
| Package / Case | TQFP-144 | Number Of Logic Elements/cells | * |
| Number Of Labs/clbs | * | Total Ram Bits | 226304 |
| Number Of I /o | 100 | Number Of Gates | - |
| Voltage - Supply | 1.14 V ~ 1.26 V | Mounting Type | * |
| Operating Temperature | -40°C ~ 100°C | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
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PrevNext
May 2007
For Further Information
A variety of technical notes for the LatticeXP2 FPGA family are available on the Lattice Semiconductor web site at
www.latticesemi.com.
• TN1136,
LatticeXP2 sysIO Usage Guide
• TN1137,
LatticeXP2 Memory Usage Guide
• TN1138,
LatticeXP2 High Speed I/O Interface
• TN1126,
LatticeXP2 sysCLOCK PLL Design and Usage Guide
• TN1139,
Power Estimation and Management for LatticeXP2 Devices
• TN1140,
LatticeXP2 sysDSP Usage Guide
• TN1141,
LatticeXP2 sysCONFIG Usage Guide
• TN1142,
LatticeXP2 Configuration Encryption and Security Usage Guide
• TN1087,
Minimizing System Interruption During Configuration Using TransFR Technology
• TN1220,
LatticeXP2 Dual Boot Feature
• TN1130,
LatticeXP2 Soft Error Detection (SED) Usage Guide
• TN1143,
LatticeXP2 Hardware Checklist
For further information on interface standards refer to the following websites:
• JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org
• PCI: www.pcisig.com
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
LatticeXP2 Family Data Sheet
Supplemental Information
6-1
Data Sheet DS1009
Further Info_01.1
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