LFXP2-8E-5TN144I | |
|---|---|
| Manufacturer Part Number | LFXP2-8E-5TN144I |
| Description | FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd |
| Manufacturer | Lattice |
| LFXP2-8E-5TN144I datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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Specifications of LFXP2-8E-5TN144I | |||
|---|---|---|---|
| Number Of Macrocells | 8000 | Number Of Programmable I/os | 100 |
| Data Ram Size | 226304 | Supply Voltage (max) | 1.26 V |
| Maximum Operating Temperature | + 100 C | Minimum Operating Temperature | - 40 C |
| Mounting Style | SMD/SMT | Supply Voltage (min) | 1.14 V |
| Package / Case | TQFP-144 | Number Of Logic Elements/cells | * |
| Number Of Labs/clbs | * | Total Ram Bits | 226304 |
| Number Of I /o | 100 | Number Of Gates | - |
| Voltage - Supply | 1.14 V ~ 1.26 V | Mounting Type | * |
| Operating Temperature | -40°C ~ 100°C | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
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PrevNext
April 2011
Revision History
Date
Version
May 2007
01.1
September 2007
01.2
DC and Switching
Characteristics
Pinout Information
February 2008
01.3
Architecture
DC and Switching
Characteristics
Pinout Information
Ordering Information
April 2008
01.4
DC and Switching
Characteristics
© 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
LatticeXP2 Family Data Sheet
Section
—
Initial release.
Added JTAG Port Timing Waveforms diagram.
Updated sysCLOCK PLL Timing table.
Added Thermal Management text section.
Added LVCMOS33D to Supported Output Standards table.
Clarified: “This Flash can be programmed through either the JTAG or
Slave SPI ports of the device. The SRAM configuration space can also
be infinitely reconfigured through the JTAG and Master SPI ports.”
Added External Slave SPI Port to Serial TAG Memory section. Updated
Serial TAG Memory diagram.
Updated Flash Programming Specifications table.
Added “8W” specification to Hot Socketing Specifications table.
Updated Timing Tables
Clarifications for IIH in DC Electrical Characteristics table.
Added LVCMOS33D section
Updated DOA and DOA (Regs) to EBR Timing diagrams.
Removed Master Clock Frequency and Duty Cycle sections from the
LatticeXP2 sysCONFIG Port Timing Specifications table. These are
listed on the On-chip Oscillator and Configuration Master Clock Charac-
teristics table.
Changed CSSPIN to CSSPISN in description of t
parameters. Removed t
Clarified On-chip Oscillator documentation
Added Switching Test Conditions
Added “True LVDS Pairs Bonding Out per Bank,” “DDR Banks Bonding
Out per I/O Bank,” and “PCI capable I/Os Bonding Out per Bank” to Pin
Information Summary in place of previous blank table “PCI and DDR
Capabilities of the Device-Package Combinations”
Removed pinout listing. This information is available on the LatticeXP2
product web pages
Added XP2-17 “8W” and all other family OPNs.
Updated Absolute Maximum Ratings footnotes.
Updated Recommended Operating Conditions Table footnotes.
Updated Supply Current (Standby) Table
Updated Initialization Supply Current Table
Updated Programming and Erase Flash Supply Current Table
Updated Register to Register Performance Table
Updated LatticeXP2 External Switching Characteristics Table
Updated LatticeXP2 Internal Switching Characteristics Table
Updated sysCLOCK PLL Timing Table
7-1
Revision History
Data Sheet DS1009
Change Summary
, t
, and t
SCS
SCSS
parameter.
SOE
SCSH
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