LFXP2-8E-5TN144I | |
|---|---|
| Manufacturer Part Number | LFXP2-8E-5TN144I |
| Description | FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd |
| Manufacturer | Lattice |
| LFXP2-8E-5TN144I datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
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Specifications of LFXP2-8E-5TN144I | |||
|---|---|---|---|
| Number Of Macrocells | 8000 | Number Of Programmable I/os | 100 |
| Data Ram Size | 226304 | Supply Voltage (max) | 1.26 V |
| Maximum Operating Temperature | + 100 C | Minimum Operating Temperature | - 40 C |
| Mounting Style | SMD/SMT | Supply Voltage (min) | 1.14 V |
| Package / Case | TQFP-144 | Number Of Logic Elements/cells | * |
| Number Of Labs/clbs | * | Total Ram Bits | 226304 |
| Number Of I /o | 100 | Number Of Gates | - |
| Voltage - Supply | 1.14 V ~ 1.26 V | Mounting Type | * |
| Operating Temperature | -40°C ~ 100°C | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
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PrevNext
Lattice Semiconductor
Date
Version
April 2008
01.4
DC and Switching
(cont.)
(cont.)
Characteristics (cont.)
Pinout Information
June 2008
01.5
Architecture
DC and Switching
Characteristics
Pinout Information
August 2008
01.6
Architecture
DC and Switching
Characteristics
Ordering Information
April 2011
01.7
DC and Switching
Characteristics
Section
Updated Flash Download Time (From On-Chip Flash to SRAM) Table
Updated Flash Program Time Table
Updated Flash Erase Time Table
Updated FlashBAK (from EBR to Flash) Table
Updated Hot Socketing Specifications Table footnotes
Updated Signal Descriptions Table
Removed Read-Before-Write sysMEM EBR mode.
Clarification of the operation of the secondary clock regions.
Removed Read-Before-Write sysMEM EBR mode.
Updated DDR Banks Bonding Out per I/O Bank section of Pin Informa-
tion Summary Table.
—
Data sheet status changed from preliminary to final.
Clarification of the operation of the secondary clock regions.
Removed “8W” specification from Hot Socketing Specifications table.
Removed "8W" footnote from DC Electrical Characteristics table.
Updated Register-to-Register Performance table.
Removed “8W” option from Part Number Description.
Removed XP2-17 “8W” OPNs.
Recommended Operating Conditions table, added footnote 5.
On-Chip Flash Memory Specifications table, added footnote 1.
BLVDS DC Conditions, corrected column title to be Z0 = 90 ohms.
sysCONFIG Port Timing Specifications table, added footnote 1 for
t
.
DINIT
7-2
Revision History
LatticeXP2 Family Data Sheet
Change Summary
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