LFXP2-8E-5TN144I | |
|---|---|
| Manufacturer Part Number | LFXP2-8E-5TN144I |
| Description | FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd |
| Manufacturer | Lattice |
| LFXP2-8E-5TN144I datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
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Specifications of LFXP2-8E-5TN144I | |||
|---|---|---|---|
| Number Of Macrocells | 8000 | Number Of Programmable I/os | 100 |
| Data Ram Size | 226304 | Supply Voltage (max) | 1.26 V |
| Maximum Operating Temperature | + 100 C | Minimum Operating Temperature | - 40 C |
| Mounting Style | SMD/SMT | Supply Voltage (min) | 1.14 V |
| Package / Case | TQFP-144 | Number Of Logic Elements/cells | * |
| Number Of Labs/clbs | * | Total Ram Bits | 226304 |
| Number Of I /o | 100 | Number Of Gates | - |
| Voltage - Supply | 1.14 V ~ 1.26 V | Mounting Type | * |
| Operating Temperature | -40°C ~ 100°C | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
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PrevNext
Lattice Semiconductor
LatticeXP2 Memory Usage Guide
Figure 10-3. Example Generating Pseudo Dual Port RAM (RAM_DP) Using IPexpress
In the right pane, options like the Device Family, Macro Type, Category, and Module_Name are device and
selected module dependent. These cannot be changed in IPexpress.
Users can change the directory where the generated module files will be placed by clicking the Browse button in
the Project Path.
The Module Name text box allows users to specify an entity name for the module they are about to generate.
Users must provide this entity name.
Design entry, Verilog or VHDL, by default, is the same as the project type. If the project is a VHDL project, the
selected design entry option will be “Schematic/ VHDL”, and “Schematic/ Verilog-HDL” if the project type is Verilog-
HDL.
The Device pull-down menu allows users to select different devices within the same family, LatticeXP2 in this
example. By clicking the Customize button, another window opens where users can customize the RAM
(Figure 10-4).
10-4
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