LFXP2-8E-5TN144I

Manufacturer Part NumberLFXP2-8E-5TN144I
DescriptionFPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
ManufacturerLattice
LFXP2-8E-5TN144I datasheets

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Specifications of LFXP2-8E-5TN144I

Number Of Macrocells8000Number Of Programmable I/os100
Data Ram Size226304Supply Voltage (max)1.26 V
Maximum Operating Temperature+ 100 CMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTSupply Voltage (min)1.14 V
Package / CaseTQFP-144Number Of Logic Elements/cells*
Number Of Labs/clbs*Total Ram Bits226304
Number Of I /o100Number Of Gates-
Voltage - Supply1.14 V ~ 1.26 VMounting Type*
Operating Temperature-40°C ~ 100°CLead Free Status / RoHS StatusLead free / RoHS Compliant
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Lattice Semiconductor
Table 10-2. EBR-based Single Port Memory Port Definitions
Port Name in
Generated Module
Clock
ClockEn
Address
Data
Q
WE
Reset
—
Reset (or RST) resets only the input and output registers of the RAM. It does not reset the contents of the memory.
Chip Select (CS) is a useful port in the EBR primitive when multiple cascaded EBR blocks are required by the
memory. The CS signal forms the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-bit bus,
so it can cascade eight memories easily. If the memory size specified by the user requires more than eight EBR
blocks, the ispLEVER software automatically generates the additional address decoding logic, which is imple-
mented in the PFU (external to the EBR blocks).
Each EBR block consists of 18,432 bits of RAM. The values for x (address) and y (data) for each EBR block for the
devices are listed in Table 10-3.
Table 10-3. Single Port Memory Sizes for 16K Memories for LatticeXP2
Single Port
Memory Size
16K x 1
8K x 2
4K x 4
2K x 9
1K x 18
512 x 36
Table 10-4 shows the various attributes available for the Single Port Memory (RAM_DQ). Some of these attributes
are user-selectable through the IPexpress GUI. For detailed attribute definitions, refer to Appendix A.
Port Name in the
EBR Block Primitive
Description
CLK
Clock
CE
Clock Enable
AD[x:0]
Address Bus
DI[y:0]
Data In
DO[y:0]
Data Out
WE
Write Enable
RST
Reset
CS[2:0]
Chip Select
Input Data
Output Data
DI
DO
DI[1:0]
DO[1:0]
DI[3:0]
DO[3:0]
DI[8:0]
DO[8:0]
DI[17:0]
DO[17:0]
DI[35:0]
DO[35:0]
10-7
LatticeXP2 Memory Usage Guide
Active State
Rising Clock Edge
Active High
—
—
—
Active High
Active High
—
Address [MSB:LSB]
AD[13:0]
AD[12:0]
AD[11:0]
AD[10:0]
AD[9:0]
AD[8:0]

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