LFXP2-8E-5TN144I | |
|---|---|
| Manufacturer Part Number | LFXP2-8E-5TN144I |
| Description | FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd |
| Manufacturer | Lattice |
| LFXP2-8E-5TN144I datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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Specifications of LFXP2-8E-5TN144I | |||
|---|---|---|---|
| Number Of Macrocells | 8000 | Number Of Programmable I/os | 100 |
| Data Ram Size | 226304 | Supply Voltage (max) | 1.26 V |
| Maximum Operating Temperature | + 100 C | Minimum Operating Temperature | - 40 C |
| Mounting Style | SMD/SMT | Supply Voltage (min) | 1.14 V |
| Package / Case | TQFP-144 | Number Of Logic Elements/cells | * |
| Number Of Labs/clbs | * | Total Ram Bits | 226304 |
| Number Of I /o | 100 | Number Of Gates | - |
| Voltage - Supply | 1.14 V ~ 1.26 V | Mounting Type | * |
| Operating Temperature | -40°C ~ 100°C | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
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PrevNext
Lattice Semiconductor
Figure 10-50. READ_ID Waveform
CS
CLK
SI
SO
8 Bits READ_ID
Command
WRITE_EN (ACh)
The WRITE_EN command enables the TAG memory for programming. If the WRITE_EN command has not been
shifted into the device first, the PROGRAM_TAG, ERASE_TAG and STATUS commands do not take effect. This is
to prevent the TAG memory from erroneous erase or program.
The command is executed when the Chip Select pin is driven from low to high after the 24th dummy clock. Any
extra dummy clocks, if presented before driving the Chip Select pin to high, are ignored. After the Chip Select pin is
driven from low to high, a minimum of three clocks are required to complete the execution of the command.
The effect of this command is terminated by the WRITE_DIS command.
Figure 10-51. WRITE_EN Waveform
CS
CLK
SI
SO
WRITE_DIS (78h)
The WRITE_DIS command disables the TAG memory for programming. It does not nullify the READ_TAG and
READ_ID commands.
The command is executed when the Chip Select pin is driven from low to high after the 24th dummy clock. Any
extra dummy clocks, if presented before driving the Chip Select pin to high, are ignored. After the Chip Select pin is
driven from low to high, a minimum of three clocks are required to complete the execution of the command.
HI-Z
0 1 2
32 Bits JTAG IDCODE
24 Bits Dummy
Optional Extra Clocks
3 Clocks To Initiate And Complete
HIGH IMPEDANCE
8 Command
Shifting Clocks
10-45
LatticeXP2 Memory Usage Guide
HI-Z
31
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