LFXP2-8E-5TN144I | |
|---|---|
| Manufacturer Part Number | LFXP2-8E-5TN144I |
| Description | FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd |
| Manufacturer | Lattice |
| LFXP2-8E-5TN144I datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
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Specifications of LFXP2-8E-5TN144I | |||
|---|---|---|---|
| Number Of Macrocells | 8000 | Number Of Programmable I/os | 100 |
| Data Ram Size | 226304 | Supply Voltage (max) | 1.26 V |
| Maximum Operating Temperature | + 100 C | Minimum Operating Temperature | - 40 C |
| Mounting Style | SMD/SMT | Supply Voltage (min) | 1.14 V |
| Package / Case | TQFP-144 | Number Of Logic Elements/cells | * |
| Number Of Labs/clbs | * | Total Ram Bits | 226304 |
| Number Of I /o | 100 | Number Of Gates | - |
| Voltage - Supply | 1.14 V ~ 1.26 V | Mounting Type | * |
| Operating Temperature | -40°C ~ 100°C | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
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PrevNext
Lattice Semiconductor
Figure 11-34. IDDRX2B Waveform
CLK at I/O
P0
DDR DATA at I/O
ECLK (shifted 90 deg)
P0
DDR DATA at IDDRX2B
A
B
XX
XX
C
D/E
F/G
SCLK
QB1
QA1
QB0
QB1
ODDRXC
This is the DDR output module. This primitive will input two data streams and mux them together to generate a sin-
gle stream of data going to the sysIO™ buffer. The CLK to this module can be connected to the edge clock or to the
FPGA clock. This primitive is also used for when DDR function is required for the tristate signal.
Figure 11-35 shows the primitive symbol for the ODDRXC mode.
Figure 11-35. ODDRXC Symbol
Table 11-9 lists the port names and descriptions for the ODDRXC primitive.
LatticeXP2 High-Speed I/O Interface
P2
N0
P1
N1
N0
P1
N1
P2
P1
P0
N1
N0
P1
P0
P1/N1
XX
P0/N0
XX
P0/N0
XX
XX
XX
XX
ODDRXC
CLK
Q
DA
DB
RST
11-29
N2
P3
N3
P4
N2
P3
N4
N3
P4
P2
P3
P4
N2
N3
P2
P3
P2/N2
P3/N3
P1/N1
P2/N2
P0
P1
N0
N1
N4
P4
P2
P3
N2
N3
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