LFXP2-8E-5TN144I | |
|---|---|
| Manufacturer Part Number | LFXP2-8E-5TN144I |
| Description | FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd |
| Manufacturer | Lattice |
| LFXP2-8E-5TN144I datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
×
Shipping terms
- Standard delivery time differs from 5-8 business days if the supplier is a local one to 12-14 days if the suplier is from overseas. If delivery time differs it's always mentioned in our quotation.
- We ship worldwide using main international couriers like FedEx, DHL, UPS, TNT, EMS. We can also use client's freight account. Other shipping methods can be discussed. We do best to meet your needs!
Payment terms
- For new client payment term is payment in advance. At this moment we accept 3 payment methods: wire transfer, PayPal and Western Union. Credit card payment is under constrution and will be introduced soon. Escrow service is acceptable. Net terms for regular customers is not a problem. Working with us is totally safe for you.
- If you still have any questions - please contact us
Specifications of LFXP2-8E-5TN144I | |||
|---|---|---|---|
| Number Of Macrocells | 8000 | Number Of Programmable I/os | 100 |
| Data Ram Size | 226304 | Supply Voltage (max) | 1.26 V |
| Maximum Operating Temperature | + 100 C | Minimum Operating Temperature | - 40 C |
| Mounting Style | SMD/SMT | Supply Voltage (min) | 1.14 V |
| Package / Case | TQFP-144 | Number Of Logic Elements/cells | * |
| Number Of Labs/clbs | * | Total Ram Bits | 226304 |
| Number Of I /o | 100 | Number Of Gates | - |
| Voltage - Supply | 1.14 V ~ 1.26 V | Mounting Type | * |
| Operating Temperature | -40°C ~ 100°C | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
PrevNext
Lattice Semiconductor
Control Logic Block ................................................................................................................................. 2-30
DDR Memory Support...................................................................................................................................... 2-30
DLL Calibrated DQS Delay Block ........................................................................................................... 2-32
Polarity Control Logic .............................................................................................................................. 2-33
DQSXFER............................................................................................................................................... 2-34
sysIO Buffer ..................................................................................................................................................... 2-34
sysIO Buffer Banks ................................................................................................................................. 2-34
Typical sysIO I/O Behavior During Power-up.......................................................................................... 2-35
Supported sysIO Standards .................................................................................................................... 2-35
Hot Socketing.......................................................................................................................................... 2-37
IEEE 1149.1-Compliant Boundary Scan Testability......................................................................................... 2-37
flexiFLASH Device Configuration..................................................................................................................... 2-38
Serial TAG Memory................................................................................................................................. 2-39
Live Update Technology ......................................................................................................................... 2-39
Soft Error Detect (SED) Support ............................................................................................................. 2-40
On-Chip Oscillator................................................................................................................................... 2-40
Density Shifting ................................................................................................................................................ 2-41
DC and Switching Characteristics
Absolute Maximum Ratings ............................................................................................................................... 3-1
Recommended Operating Conditions ................................................................................................................ 3-1
On-Chip Flash Memory Specifications............................................................................................................... 3-1
Hot Socketing Specifications.............................................................................................................................. 3-2
DC Electrical Characteristics.............................................................................................................................. 3-2
Supply Current (Standby)................................................................................................................................... 3-3
Initialization Supply Current ............................................................................................................................... 3-4
Programming and Erase Flash Supply Current ................................................................................................. 3-5
sysIO Recommended Operating Conditions...................................................................................................... 3-6
sysIO Single-Ended DC Electrical Characteristics............................................................................................. 3-7
sysIO Differential Electrical Characteristics ....................................................................................................... 3-8
LVDS......................................................................................................................................................... 3-8
Differential HSTL and SSTL...................................................................................................................... 3-8
LVDS25E .................................................................................................................................................. 3-8
LVCMOS33D ............................................................................................................................................ 3-9
BLVDS .................................................................................................................................................... 3-10
LVPECL .................................................................................................................................................. 3-11
RSDS ...................................................................................................................................................... 3-12
MLVDS.................................................................................................................................................... 3-13
Typical Building Block Function Performance.................................................................................................. 3-14
Pin-to-Pin Performance (LVCMOS25 12mA Drive) ................................................................................ 3-14
Register-to-Register Performance .......................................................................................................... 3-14
Derating Timing Tables .................................................................................................................................... 3-15
LatticeXP2 External Switching Characteristics ................................................................................................ 3-16
LatticeXP2 Internal Switching Characteristics.................................................................................................. 3-19
EBR Timing Diagrams...................................................................................................................................... 3-22
LatticeXP2 Family Timing Adders .................................................................................................................... 3-24
sysCLOCK PLL Timing .................................................................................................................................... 3-27
LatticeXP2 sysCONFIG Port Timing Specifications......................................................................................... 3-28
On-Chip Oscillator and Configuration Master Clock Characteristics................................................................ 3-29
Flash Download Time (from On-Chip Flash to SRAM) .................................................................................... 3-30
Flash Program Time......................................................................................................................................... 3-30
Flash Erase Time ............................................................................................................................................. 3-30
FlashBAK Time (from EBR to Flash) ............................................................................................................... 3-31
JTAG Port Timing Specifications ..................................................................................................................... 3-31
Switching Test Conditions................................................................................................................................ 3-33
LatticeXP2 Family Handbook
2
Table of Contents
Related parts for LFXP2-8E-5TN144I | |||
|---|---|---|---|
| Part Number | Description | Manufacturer | Datasheet |
 LFXP2-8E-5TN144C |
FPGA - Field Programmable Gate Array 8K LUTs 100I/O Inst- on DSP 1.2V -5 Spd | Lattice |
|
 LFXP2-8E-5FTN256C |
IC, LATTICEXP2 FPGA, 435MHZ, FTBGA-256 | LATTICE SEMICONDUCTOR |
|
 LFXP2-8E-5QN208C |
IC, LATTICEXP2 FPGA, 435MHZ, QFP-208 | LATTICE SEMICONDUCTOR |
|
 LFXP2-8E-5FTN256I |
FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd | Lattice |
|
 LFXP2-8E-7TN144C |
FPGA LatticeXP2 Family 8000 Cells Flash Technology 1.2V 144-Pin TQFP | LATTICE SEMICONDUCTOR |
|
|
LFXP2-8E-7FT256C |
FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -7 Spd | Lattice |
|
 LFXP2-8E-6QN208C |
IC DSP 8KLUTS 146I/O 208PQFP | Lattice |
|
|
LFXP2-8E-6TN144C |
IC DSP 8KLUTS 100I/O 144TQFP | Lattice |
|
|
LFXP2-8E-6MN132C |
IC DSP 8KLUTS 86I/O 132CSBGA | Lattice |
|
|
LFXP2-8E-5MN132I |
IC DSP 8KLUTS 86I/O 132CSBGA | Lattice |
|
|
LFXP2-8E-5QN208I |
IC DSP 8KLUTS 146I/O 208PQFP | Lattice |
|
|
LFXP2-8E-6FTN256C |
IC DSP 8KLUTS 201I/O 256FTBGA | Lattice |
|
|
LFXP2-8E-5MG132C |
IC FPGA 8KLUTS 86I/O 132-BGA | Lattice |
|
|
LFXP2-8E-5M132I |
IC FPGA 8KLUTS 86I/O 132-BGA | Lattice |
|
|
LFXP2-8E-5FT256C |
IC FPGA 8KLUTS 201I/O 256-BGA | Lattice |
|
