LFXP2-8E-5TN144I | |
|---|---|
| Manufacturer Part Number | LFXP2-8E-5TN144I |
| Description | FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd |
| Manufacturer | Lattice |
| LFXP2-8E-5TN144I datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
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Specifications of LFXP2-8E-5TN144I | |||
|---|---|---|---|
| Number Of Macrocells | 8000 | Number Of Programmable I/os | 100 |
| Data Ram Size | 226304 | Supply Voltage (max) | 1.26 V |
| Maximum Operating Temperature | + 100 C | Minimum Operating Temperature | - 40 C |
| Mounting Style | SMD/SMT | Supply Voltage (min) | 1.14 V |
| Package / Case | TQFP-144 | Number Of Logic Elements/cells | * |
| Number Of Labs/clbs | * | Total Ram Bits | 226304 |
| Number Of I /o | 100 | Number Of Gates | - |
| Voltage - Supply | 1.14 V ~ 1.26 V | Mounting Type | * |
| Operating Temperature | -40°C ~ 100°C | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
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PrevNext
Lattice Semiconductor
One Shot SED in VHDL
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity example is
port (
sed_done : out std_logic;
sed_in_prog : out std_logic;
sed_out : out std_logic);
end;
architecture behavioral of example is
component SEDBB -- This is for One Shot SED
generic (OSC_DIV : integer := 1); -- set SEDCLKIN divider
port (
SEDDONE : out std_logic;
SEDINPROG : out std_logic;
SEDERR : out std_logic
);
end component;
begin
isnt1: SEDBB
generic map (OSC_DIV=> “1”)
port map (
SEDERR => sed_out, -- wired to an output
SEDDONE => sed_done, -- wired to an output
SEDINPROG => sed_in_prog); -- wired to an output
end behavioral ;
LatticeXP2 Soft Error
Detection Usage Guide
16-7
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