LFXP2-8E-5TN144I

Manufacturer Part NumberLFXP2-8E-5TN144I
DescriptionFPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
ManufacturerLattice
LFXP2-8E-5TN144I datasheets

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Specifications of LFXP2-8E-5TN144I

Number Of Macrocells8000Number Of Programmable I/os100
Data Ram Size226304Supply Voltage (max)1.26 V
Maximum Operating Temperature+ 100 CMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTSupply Voltage (min)1.14 V
Package / CaseTQFP-144Number Of Logic Elements/cells*
Number Of Labs/clbs*Total Ram Bits226304
Number Of I /o100Number Of Gates-
Voltage - Supply1.14 V ~ 1.26 VMounting Type*
Operating Temperature-40°C ~ 100°CLead Free Status / RoHS StatusLead free / RoHS Compliant
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Download datasheet (10Mb)Embed
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Lattice Semiconductor
ispVM System and ispVME takes care of the detail to program the SPI Flash devices via the JTAG port. The detail
task is shown in the waveform diagram on on
Table 17-7. Description of the Hare-wired JTAG SPI Flash Programming IP
Block #
Title
1
Reset JTAG Port
The standard method to set the JTAG state machine to a known state.
Shift in the PROGRAM_SPI instruction (OPCODE = 0x0X).  Indicate bit 0 first shifting direction.
2
Send Instruction
3
Connect
The 4-pin JTAG port is connected to the 4-pin SPI interface. SLCK following TCK indicate
connection is made.
4
Repeat
Loop around to erase by sectors and programming by pages.
5
Shift Data
Send in the command to erase a sector or shift in one page of programming data. The FPGA
respond by driving the CSSPIN pin to low to gate on SCLK, SPID0, and SISPI.
6
Burn Time Delay
Drive the CSSPIN to high to command the SPI Flash device to start the erase or program-
ming action. Wait for the required erase or programming delay time then poll the complete
status. Consult the SPI Flash datasheet for the polling method required.
Figure 17-4. Waveform Diagram of the Hare-wired JTAG SPI Flash Programming IP
1
TLR
RTI DRS IRS CIR
???
???
TLR
RTI DRS IRS CTR
5
TCK
TMS
TDI
TDO
CCSPIN
SCLK
SIPI
SPISO
References
• Lattice Technical Note TN1087,
• Lattice Technical Note TN1141,
• Lattice Technical Note TN1142,
Description
3
2
SIR
UIR RTI DRS CDR
E1IR
STR
UIR RTI DRS CDR
E1IR
7
Minimizing System Interruption During Configuration Using TransFR Technology
LatticeXP2 sysCONFIG Usage Guide
LatticeXP2 Configuration Encryption and Security Usage Guide
17-15
LatticeXP2 Dual Boot Feature
4
SDR
PDR
E1DR
E2DR
SDR
PDR
IRS TLR
E2DR UDR DRS
E1DR
N-1
N-1
6
5

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