LFXP2-8E-5TN144I

Manufacturer Part NumberLFXP2-8E-5TN144I
DescriptionFPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
ManufacturerLattice
LFXP2-8E-5TN144I datasheets

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Specifications of LFXP2-8E-5TN144I

Number Of Macrocells8000Number Of Programmable I/os100
Data Ram Size226304Supply Voltage (max)1.26 V
Maximum Operating Temperature+ 100 CMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTSupply Voltage (min)1.14 V
Package / CaseTQFP-144Number Of Logic Elements/cells*
Number Of Labs/clbs*Total Ram Bits226304
Number Of I /o100Number Of Gates-
Voltage - Supply1.14 V ~ 1.26 VMounting Type*
Operating Temperature-40°C ~ 100°CLead Free Status / RoHS StatusLead free / RoHS Compliant
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Lattice Semiconductor
Table 18-3. Configuration Pin Descriptions
Pin Name
CFG0
Input, weak pull-up
CFG1
Input, weak pull-up
PROGRAMN Input, weak pull-up
INITN
Bi-Directional Open Drain, weak pull-up
DONE
Bi-Directional Open Drain with weak pull-up or Active Drive
CCLK
Input or Output
SISPI
Input or Output
SOSPI
Input or Output
CSSPISN
Input, weak pull-up
CSSPIN
Output, tri-state, weak pull-up
JTAG Interface
The JTAG interface pins are referenced to V
port supplies from 1.2V to 3.3V. In cases where V
JTAG interface cable or tester can support I/O interface with the same I/O voltage standard.
I/O Interface and Critical Pins
There are eight I/O banks on every LatticeXP2 device. I/O Bank 7 contains the configuration pins and as such, the
configuration requirements should have the highest priority to determine the supply voltage levels for V
I/O Pin Assignments Around V
The V
provides a “quiet” supply for the internal PLLs. For the best PLL jitter performance, careful pin assign-
CCPLL
ment must keep away the “noisy” I/O pins away from the BGA ball location that are identified as sensitive pins as
shown in Figure 18-1. In this case the sensitive pins would be one of the V
are generally defined to have the highest switching frequency, highest V
rates. For example, using the Figure 18-1 3x3 and 5x5 grid of ball locations, one can identify the “keep out” ball
locations for the potentially “noisy” signals. Note: In fpBGA and ftBGA packages, V
own pins; it is connected to the V
Figure 18-1. “Quiet” Pin Assignment Consideration for BGA Package
I/O Type
. Typically, JTAG pins are referenced to 3.3V supply. V
CCJ
is connected to supplies other than 3.3V, validate that the
CCJ
CCPLL
pins. In this case, this discussion applies to the V
CCAUX
5x5
5x5
5x5
5x5
3x3
3x3
Sensitive
5x5
3x3
Pin
5x5
3x3
3x3
5x5
5x5
5x5
18-3
LatticeXP2 Hardware Checklist
Pin Type
Description
Dedicated
FPGA configuration mode
selection
Dual-Purpose
Dual-Purpose
FPGA Configuration 
Dual-Purpose
control and status signals
Dual-Purpose
Dual-Purpose
Configuration clock
Dual-Purpose
SPI control and data 
Dual-Purpose
signals
Dual-Purpose
Dual-Purpose
supply pins. The “noisy” I/O pins
CCPLL
standard and fastest output slew
CCIO
is not provided from its
CCPLL
pins.
CCAUX
5x5
5x5
3x3
5x5
3x3
5x5
3x3
5x5
5x5
5x5
can sup-
CCJ
.
CCIO7

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