LFXP2-8E-5TN144I

Manufacturer Part NumberLFXP2-8E-5TN144I
DescriptionFPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
ManufacturerLattice
LFXP2-8E-5TN144I datasheets

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Specifications of LFXP2-8E-5TN144I

Number Of Macrocells8000Number Of Programmable I/os100
Data Ram Size226304Supply Voltage (max)1.26 V
Maximum Operating Temperature+ 100 CMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTSupply Voltage (min)1.14 V
Package / CaseTQFP-144Number Of Logic Elements/cells*
Number Of Labs/clbs*Total Ram Bits226304
Number Of I /o100Number Of Gates-
Voltage - Supply1.14 V ~ 1.26 VMounting Type*
Operating Temperature-40°C ~ 100°CLead Free Status / RoHS StatusLead free / RoHS Compliant
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Lattice Semiconductor
LatticeXP2 Hardware Checklist
DDR/DDR2 Memory Interface Pin Assignments
The DDR Memory interface on the LatticeXP2 device family is provided with a pre-engineered I/O register along
with the precision I/O DLL timing control. There are two I/O DLL specifically assigned to the two halves of the
device. One I/O DLL supports I/O banks 1, 2, 3 and 4; another I/O DLL supports I/O banks 0, 5, 6 and 7.
In addition to the I/O DLL assignments, there are pre-defined data strobes (DQS) signals that can support a span
of I/O pins as part of the memory data lanes. When assigning DDR memory interface I/O pins, the FPGA designer
must insure that there is enough I/O pins to assign DDR memory data pins for each of the assigned DQS signals.
True-LVDS Output Pin Assignments
True-LVDS outputs are available on 50% of the I/O pins on the left and right sides of the device. The left and right
side I/O banks are banks 2, 3, 6 and 7. When using the LVDS outputs, a 2.5V supply needs to be connected to
these VCCIO supply rails.
HSTL and SSTL Pin Assignments
These externally referenced I/O standards require an external reference voltage. Each of the LatticeXP2 device
family I/O banks allows up to two pre-defined V
pins. The V
pin(s) should get the highest priority for pin
REF
REF
assignment.
PCI Clamp Pin Assignment
PCI clamps are available on the top and bottom sides of the device. When the system design calls for PCI clamp,
those pins should be assigned to I/O banks 0, 1, 4 and 5. For the clamp characteristic, refer to the IBIS buffer mod-
els either on the Lattice website at
www.latticesemi.com
or in the ispLEVER design tool.
Test Output Enable (TOE)
TOE signal is used to tri-state all I/O pins and override the functional outputs for board level test. It is recommended
to have a pull-up resistor to make sure that when not in use, the TOE will not interfere with the normal functionality
of the I/O pins.
18-4

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