LFXP2-8E-5TN144I

Manufacturer Part NumberLFXP2-8E-5TN144I
DescriptionFPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
ManufacturerLattice
LFXP2-8E-5TN144I datasheets

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Specifications of LFXP2-8E-5TN144I

Number Of Macrocells8000Number Of Programmable I/os100
Data Ram Size226304Supply Voltage (max)1.26 V
Maximum Operating Temperature+ 100 CMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTSupply Voltage (min)1.14 V
Package / CaseTQFP-144Number Of Logic Elements/cells*
Number Of Labs/clbs*Total Ram Bits226304
Number Of I /o100Number Of Gates-
Voltage - Supply1.14 V ~ 1.26 VMounting Type*
Operating Temperature-40°C ~ 100°CLead Free Status / RoHS StatusLead free / RoHS Compliant
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PrevNext
Lattice Semiconductor
IPexpress™
The user can access the sysDSP block via the ispLEVER IPexpress tool, which provides the option to configure
each DSP module (or group of modules), or by direct HDL instantiation. In addition, Lattice has partnered with The
®
MathWorks
to support instantiation in the Simulink
ispLEVER to dramatically shorten the DSP design cycle in Lattice FPGAs.
Optimized DSP Functions
Lattice provides a library of optimized DSP IP functions. Some of the IP cores planned for the LatticeXP2 DSP
include the Bit Correlator, FFT functions, FIR Filter, Reed-Solomon Encoder/Decoder, Turbo Encoder/Decoder and
Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available DSP IP cores.
Resources Available in the LatticeXP2 Family
Table 2-8 shows the maximum number of multipliers for each member of the LatticeXP2 family. Table 2-9 shows the
maximum available EBR RAM Blocks and Serial TAG Memory bits in each LatticeXP2 device. EBR blocks,
together with Distributed RAM can be used to store variables locally for fast DSP operations.
Table 2-8. Maximum Number of DSP Blocks in the LatticeXP2 Family
Device
DSP Block
XP2-5
XP2-8
XP2-17
XP2-30
XP2-40
Table 2-9. Embedded SRAM/TAG Memory in the LatticeXP2 Family
Device
XP2-5
XP2-8
XP2-17
XP2-30
XP2-40
LatticeXP2 DSP Performance
Table 2-10 lists the maximum performance in Millions of MAC (MMAC) operations per second for each member of
the LatticeXP2 family.
Table 2-10. DSP Performance
Device
XP2-5
XP2-8
XP2-17
XP2-30
XP2-40
For further information on the sysDSP block, please see TN1140,
®
tool, a graphical simulation environment. Simulink works with
9x9 Multiplier
3
24
4
32
5
40
7
56
8
64
Total EBR SRAM
EBR SRAM Block
(Kbits)
9
12
15
21
48
DSP Block
3
4
5
7
8
LatticeXP2 sysDSP Usage
2-25
Architecture
LatticeXP2 Family Data Sheet
18x18 Multiplier
36x36 Multiplier
12
16
20
28
32
TAG Memory
(Bits)
166
632
221
768
276
2184
387
2640
885
3384
DSP Performance
MMAC
3,900
5,200
6,500
9,100
10,400
Guide.
3
4
5
7
8

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