LFXP2-8E-5TN144I

Manufacturer Part NumberLFXP2-8E-5TN144I
DescriptionFPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
ManufacturerLattice
LFXP2-8E-5TN144I datasheets

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Specifications of LFXP2-8E-5TN144I

Number Of Macrocells8000Number Of Programmable I/os100
Data Ram Size226304Supply Voltage (max)1.26 V
Maximum Operating Temperature+ 100 CMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTSupply Voltage (min)1.14 V
Package / CaseTQFP-144Number Of Logic Elements/cells*
Number Of Labs/clbs*Total Ram Bits226304
Number Of I /o100Number Of Gates-
Voltage - Supply1.14 V ~ 1.26 VMounting Type*
Operating Temperature-40°C ~ 100°CLead Free Status / RoHS StatusLead free / RoHS Compliant
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Lattice Semiconductor
Table 2-13. Supported Output Standards
Output Standard
Single-ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVCMOS33, Open Drain
LVCMOS25, Open Drain
LVCMOS18, Open Drain
LVCMOS15, Open Drain
LVCMOS12, Open Drain
PCI33
HSTL18 Class I, II
HSTL15 Class I
SSTL33 Class I, II
SSTL25 Class I, II
SSTL18 Class I, II
Differential Interfaces
Differential SSTL33, Class I, II
Differential SSTL25, Class I, II
Differential SSTL18, Class I, II
Differential HSTL18, Class I, II
Differential HSTL15, Class I
1, 2
LVDS
1
MLVDS
1
BLVDS
1
LVPECL
1
RSDS
1
LVCMOS33D
1. Emulated with external resistors.
2. On the left and right edges, LVDS outputs are supported with a dedicated differential output driver on 50% of the I/Os. This
solution does not require external resistors at the driver.
Hot Socketing
LatticeXP2 devices have been carefully designed to ensure predictable behavior during power-up and power-
down. Power supplies can be sequenced in any order. During power-up and power-down sequences, the I/Os
remain in tri-state until the power supply voltage is high enough to ensure reliable operation. In addition, leakage
into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of the system.
These capabilities make the LatticeXP2 ideal for many multiple power supply and hot-swap applications.
IEEE 1149.1-Compliant Boundary Scan Testability
All LatticeXP2 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access
Port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan
path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in
LatticeXP2 Family Data Sheet
Drive
4mA, 8mA, 12mA, 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA, 16mA, 20mA
4mA, 8mA, 12mA, 16mA
4mA, 8mA
2mA, 6mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA
4mA, 8mA
2mA, 6mA
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
4mA, 8mA, 12mA, 16mA, 20mA
2-37
Architecture
V
(Nom.)
CCIO
3.3
3.3
2.5
1.8
1.5
1.2
—
—
—
—
—
3.3
1.8
1.5
3.3
2.5
1.8
3.3
2.5
1.8
1.8
1.5
2.5
2.5
2.5
3.3
2.5
3.3

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