LFXP2-8E-5TN144I

Manufacturer Part NumberLFXP2-8E-5TN144I
DescriptionFPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
ManufacturerLattice
LFXP2-8E-5TN144I datasheets

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Specifications of LFXP2-8E-5TN144I

Number Of Macrocells8000Number Of Programmable I/os100
Data Ram Size226304Supply Voltage (max)1.26 V
Maximum Operating Temperature+ 100 CMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTSupply Voltage (min)1.14 V
Package / CaseTQFP-144Number Of Logic Elements/cells*
Number Of Labs/clbs*Total Ram Bits226304
Number Of I /o100Number Of Gates-
Voltage - Supply1.14 V ~ 1.26 VMounting Type*
Operating Temperature-40°C ~ 100°CLead Free Status / RoHS StatusLead free / RoHS Compliant
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Lattice Semiconductor
original backup configuration and try again. This all can be done without power cycling the system. For more
information please see TN1220,
For more information on device configuration, please see TN1141,
Soft Error Detect (SED) Support
LatticeXP2 devices have dedicated logic to perform Cyclic Redundancy Code (CRC) checks. During configuration,
the configuration data bitstream can be checked with the CRC logic block. In addition, LatticeXP2 devices can be
programmed for checking soft errors in SRAM. The SED operation can run in the background during user mode
(normal operation). In the event a soft error occurs, the device can be programmed to either reload from a known
good boot image (from internal Flash or external SPI memory) or generate an error signal.
For further information on SED support, please see TN1130,
On-Chip Oscillator
Every LatticeXP2 device has an internal CMOS oscillator that is used to derive a Master Clock (CCLK) for configu-
ration. The oscillator and CCLK run continuously and are available to user logic after configuration is complete. The
available CCLK frequencies are listed in Table 2-14. When a different CCLK frequency is selected during the
design process, the following sequence takes place:
1. Device powers up with the default CCLK frequency.
2. During configuration, users select a different CCLK frequency.
3. CCLK frequency changes to the selected frequency after clock configuration bits are received.
This internal CMOS oscillator is available to the user by routing it as an input clock to the clock tree. For further
information on the use of this oscillator for configuration or user mode, please see TN1141,
FIG Usage
Guide.
Table 2-14. Selectable CCLKs and Oscillator Frequencies During Configuration and User Mode
LatticeXP2 Dual Boot
Feature.
LatticeXP2 sysCONFIG Usage
LatticeXP2 Soft Error Detection (SED) Usage
CCLK/Oscillator (MHz)
1
2.5
2
3.1
4.3
5.4
6.9
8.1
9.2
10
13
15
20
26
32
40
54
3
80
3
163
1. Software default oscillator frequency.
2. Software default CCLK frequency.
3. Frequency not valid for CCLK.
2-40
Architecture
LatticeXP2 Family Data Sheet
Guide.
Guide.
LatticeXP2 sysCON-

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