LFXP2-8E-5TN144I

Manufacturer Part NumberLFXP2-8E-5TN144I
DescriptionFPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
ManufacturerLattice
LFXP2-8E-5TN144I datasheets

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Specifications of LFXP2-8E-5TN144I

Number Of Macrocells8000Number Of Programmable I/os100
Data Ram Size226304Supply Voltage (max)1.26 V
Maximum Operating Temperature+ 100 CMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTSupply Voltage (min)1.14 V
Package / CaseTQFP-144Number Of Logic Elements/cells*
Number Of Labs/clbs*Total Ram Bits226304
Number Of I /o100Number Of Gates-
Voltage - Supply1.14 V ~ 1.26 VMounting Type*
Operating Temperature-40°C ~ 100°CLead Free Status / RoHS StatusLead free / RoHS Compliant
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Lattice Semiconductor
LatticeXP2 sysCONFIG Port Timing Specifications
Parameter
sysCONFIG POR, Initialization and Wake Up
t
Minimum Vcc to INITN High
ICFG
t
Time from t
to valid Master CCLK
VMC
ICFG
t
PROGRAMN Pin Pulse Rejection
PRGMRJ
t
PROGRAMN Low Time to Start Configuration
PRGM
1
t
PROGRAMN High to INITN High Delay
DINIT
t
Delay Time from PROGRAMN Low to INITN Low
DPPINIT
t
Delay Time from PROGRAMN Low to DONE Low
DPPDONE
t
User I/O Disable from PROGRAMN Low
IODISS
t
User I/O Enabled Time from CCLK Edge During Wake-up Sequence
IOENSS
t
Additional Wake Master Clock Signals after DONE Pin High
MWC
sysCONFIG SPI Port (Master)
t
INITN High to CCLK Low
CFGX
t
INITN High to CSSPIN Low
CSSPI
t
CCLK Low before CSSPIN Low
CSCCLK
t
CCLK Low to Output Valid
SOCDO
t
CSSPIN[0:1] Low to First CCLK Edge Setup Time
CSPID
f
Max CCLK Frequency
MAXSPI
t
SOSPI Data Setup Time Before CCLK
SUSPI
t
SOSPI Data Hold Time After CCLK
HSPI
sysCONFIG SPI Port (Slave)
f
Slave CCLK Frequency
MAXSPIS
t
Rise and Fall Time
RF
t
Falling Edge of CCLK to SOSPI Active
STCO
t
Falling Edge of CCLK to SOSPI Disable
STOZ
t
Data Setup Time (SISPI)
STSU
t
Data Hold Time (SISPI)
STH
t
CCLK Clock Pulse Width, High
STCKH
t
CCLK Clock Pulse Width, Low
STCKL
t
Falling Edge of CCLK to Valid SOSPI Output
STVO
t
CSSPISN High Time
SCS
t
CSSPISN Setup Time
SCSS
t
CSSPISN Hold Time
SCSH
1. Re-toggling the PROGRAMN pin is not permitted until the INITN pin is high. Avoid consecutive toggling of PROGRAMN.
Over Recommended Operating Conditions
Description
3-28
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
Min
Max
—
50
—
2
—
12
50
—
—
1
—
50
—
50
—
35
—
25
0
—
—
1
—
2
0
—
—
15
2cyc
600+6cyc
—
20
7
—
10
—
—
25
50
—
—
20
—
20
8
—
10
—
0.02
200
0.02
200
—
20
25
—
25
—
25
—
Units
ms
µs
ns
ns
ms
ns
ns
ns
ns
Cycles
µs
µs
ns
ns
ns
MHz
ns
ns
MHz
mV/ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns

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