A3PN030-ZQNG68 Actel, A3PN030-ZQNG68 Datasheet - Page 55

FPGA - Field Programmable Gate Array 30K System Gates ProASIC3 nano

A3PN030-ZQNG68

Manufacturer Part Number
A3PN030-ZQNG68
Description
FPGA - Field Programmable Gate Array 30K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet

Specifications of A3PN030-ZQNG68

Processor Series
A3PN030
Core
IP Core
Number Of Macrocells
256
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
49
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
30 K
Package / Case
QFN-68
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A3PN030-ZQNG68I
Manufacturer:
ACT
Quantity:
5
Table 2-57 • Parameter Definition and Measuring Nodes
Parameter Name
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
*
OCLKQ
OSUD
OHD
OSUE
OHE
OCLR2Q
OREMCLR
ORECCLR
OECLKQ
OESUD
OEHD
OESUE
OEHE
OECLR2Q
OEREMCLR
OERECCLR
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IREMCLR
IRECCLR
See
Figure 2-11 on page 2-40
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
for more information.
Parameter Definition
R e v i s i o n 8
ProASIC3 nano Flash FPGAs
Measuring Nodes
(from, to)*
HH, DOUT
HH, EOUT
LL, DOUT
II, EOUT
GG, HH
GG, HH
CC, AA
DD, AA
KK, HH
KK, HH
AA, EE
CC, AA
BB, AA
DD, EE
DD, AA
FF, HH
FF, HH
LL, HH
LL, HH
BB, AA
JJ, HH
JJ, HH
II, HH
II, HH
2- 41

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