A3PN030-ZQNG68 Actel, A3PN030-ZQNG68 Datasheet - Page 62

FPGA - Field Programmable Gate Array 30K System Gates ProASIC3 nano

A3PN030-ZQNG68

Manufacturer Part Number
A3PN030-ZQNG68
Description
FPGA - Field Programmable Gate Array 30K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet

Specifications of A3PN030-ZQNG68

Processor Series
A3PN030
Core
IP Core
Number Of Macrocells
256
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
49
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
30 K
Package / Case
QFN-68
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A3PN030-ZQNG68I
Manufacturer:
ACT
Quantity:
5
ProASIC3 nano DC and Switching Characteristics
Figure 2-18 • Output DDR Timing Diagram
Table 2-64 • Output DDR Propagation Delays
2- 48
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
Data_F
Data_R
DDROCLKQ
DDROSUD1
DDROSUD2
DDROHD1
DDROHD2
DDROCLR2Q
DDROREMCLR
DDRORECCLR
DDROWCLR1
DDROCKMPWH
DDROCKMPWL
CLK
CLR
Out
DDOMAX
For specific junction temperature and voltage supply levels, refer to
6
Commercial-Case Conditions: T
Timing Characteristics
t
DDROCLR2Q
1
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
Data_F Data Hold for Output DDR
Data_R Data Hold for Output DDR
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width HIGH for the Output DDR
Clock Minimum Pulse Width LOW for the Output DDR
Maximum Frequency for the Output DDR
t
DDROREMCLR
t
DDROREMCLR
7
2
t
t
DDROCLKQ
DDROHD1
7
Description
J
= 70°C, Worst-Case VCC = 1.425 V
t
DDROSUD2
8
3
2
R e visio n 8
t
DDROHD2
8
Table 2-6 on page 2-5
4
9
3
350.00 350.00 350.00
t
0.38
0.36
0.32
0.70
0.38
0.00
0.00
0.80
0.00
0.22
0.22
DDRORECCLR
–2
9
0.80
0.43
0.43
0.00
0.00
0.91
0.00
0.25
0.25
0.41
0.37
10
–1
4
for derating values.
5
Std.
0.94
0.51
0.51
0.00
0.00
1.07
0.00
0.30
0.30
0.48
0.43
10
11
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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