A3PE1500-PQG208 Actel, A3PE1500-PQG208 Datasheet
A3PE1500-PQG208
Specifications of A3PE1500-PQG208
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A3PE1500-PQG208 Summary of contents
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... True Dual-Port SRAM (except ×18) • 24 SRAM and FIFO Configurations with Synchronous Operation up to 350 MHz ARM Processor Support in ProASIC3E FPGAs • M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available with or without Debug A3PE600 A3PE1500 M1A3PE1500 600,000 1,500,000 13,824 108 24 1 Yes ...
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... Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. For A3PE1500 and A3PE3000 devices, the usage of certain I/O standards is limited as follows: – SSTL3(I) and (II I/Os per north or south bank – LVPECL / GTL+ 3 GTL 3 I/Os per north or south bank – ...
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... Part Number ProASIC3E Devices A3PE600 = 600,000 System Gates A3PE1500 = 1,500,000 System Gates A3PE3000 = 3,000,000 System Gates ProASIC3E Devices with Cortex-M1 M1A3PE1500 = 1,500,000 System Gates M1A3PE3000 = 3,000,000 System Gates 896 I G Application (Temperature Range) Blank = Commercial (0°C to +70°C Ambient Temperature Industrial (–40°C to +85°C Ambient Temperature) ...
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... I = Industrial temperature range: –40°C to 85°C ambient temperature References made to ProASIC3E devices also apply to ARM-enabled ProASIC3E devices. The ARM-enabled part numbers start with M1 (Cortex-M1). Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx A3PE600 A3PE1500 M1A3PE1500 – – – – ...
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... Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-68 Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71 Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-72 Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84 JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84 Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85 Package Pin Assignments 208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 324-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 484-Pin FBGA ...
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... ProASIC3E Device Family Overview General Description ProASIC3E, the third-generation family of Actel flash FPGAs, offers performance, density, and features beyond those of the ProASIC advantage of being a secure, low power, single-chip solution that is live at power-up (LAPU). ProASIC3E is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools ...
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... This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up The Actel flash-based ProASIC3E devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The ...
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... The versatility of the ProASIC3E core tile as either a three-input lookup table (LUT) equivalent D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation architecture Flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming ...
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... LUT-3 CLK Y X3 CLR Figure 1-2 • VersaTile Configurations User Nonvolatile FlashROM Actel ProASIC3E devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: • Internet protocol addressing (wireless or fixed) • System calibration settings • Device serialization and/or inventory control • ...
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SRAM and FIFO ProASIC3E devices have embedded SRAM blocks along their north and south sides. Each variable- aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have ...
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ProASIC3E Device Family Overview Pro I/Os with Advanced I/O Standards The ProASIC3E family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). ProASIC3E FPGAs support 19 different I/O ...
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ProASIC3E DC and Switching Characteristics General Specifications DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some ...
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... ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel recommends that the user follow best design practices using Actel’s timing and power simulation tools. 7. 3.3 V wide range is compliant to the JDEC8b specification and supports 3 Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature ...
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Table 2-4 • Overshoot and Undershoot Limits Average VCCI–GND Overshoot or VCCI and VMV as a Percentage of Clock Cycle 2 less 3 V 3.3 V 3.6 V Notes: 1. Based on reliability requirements at 85°C. 2. The ...
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... ProASIC3E DC and Switching Characteristics PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLXL exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± ...
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... Thermal Characteristics Introduction The temperature variable in Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature can be used to calculate junction temperature. ...
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... HSTL (I) Notes the static power (where applicable) measured on VMV. DC2 the total dynamic power measured on V AC9 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification A3PE600 A3PE1500 105 mA 2- five times the standard I DD VMV (V) 3 ...
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Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings (continued) HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) Notes the static power (where applicable) measured on VMV. DC2 ...
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ProASIC3E DC and Switching Characteristics Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings (continued) Differential LVDS/B-LVDS/M-LVDS LVPECL Notes the static power (where applicable) measured on VMV. DC2 2. P ...
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... For a different output load, drive strength, or slew rate, Actel recommends using the Actel power calculator or ® SmartPower in Actel Libero Integrated Design Environment (IDE). ProASIC3E Flash Family FPGAs Device-Specific Dynamic Contributions (µW/MHz) A3PE600 A3PE1500 12.77 16.21 1.85 3.06 0.88 0.12 0.07 0.29 ...
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ProASIC3E DC and Switching Characteristics Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE software. The power calculation ...
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VersaTile outputs—guidelines are provided in 1 page 2- the global clock signal frequency. CLK Routing Net Contribution— NET S-CELL C-CELL N is the number of VersaTiles ...
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ProASIC3E DC and Switching Characteristics Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock percentage. If the toggle rate of a net is 100%, this means ...
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User I/O Characteristics Timing Model I/O Module (Registered 1. LVPECL 0.24 ns ICLKQ t = 0.26 ns ISUD Input LVTTL/LVCMOS Clock I/O Module (Non-Registered) LVDS, BLVDS, M-LVDS ...
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ProASIC3E DC and Switching Characteristics t PY PAD Vtrip PAD Y GND DIN GND Figure 2-3 • Input Buffer Timing Model and Delays (example CLK I/O Interface t = MAX(t (R ...
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DOUT D Q CLK D From Array I/O Interface D DOUT PAD Figure 2-4 • Output Buffer Model and Delays (example DOUT t = MAX(t (R MAX(t DOUT DOUT t t DOUT ...
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ProASIC3E DC and Switching Characteristics t EOUT D Q CLK CLK D I/O Interface D 50 EOUT (R) 50% EOUT t ZL PAD Vtrip D 50 EOUT (R) 50% EOUT t ZLS PAD ...
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... Output drive strength is below JEDEC specification. 3. Output Slew Rates can be extracted from http://www.actel.com/download/ibis/default.aspx. 4. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for normal ranges ONLY. ...
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ProASIC3E DC and Switching Characteristics Table 2-14 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions DC I/O Standards 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS ...
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Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-15 • Summary of AC Measuring Points Input Reference Voltage Standard (VREF_TYP) 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V ...
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ProASIC3E DC and Switching Characteristics Table 2-17 • Summary of I/O Timing Characteristics—Software Default Settings –2 Speed Grade, Commercial-Case Conditions: T Worst-Case V = 3.0 V CCI Equivalent Software Drive Default Strength Drive (mA) Strength Option) I/O Standard 3.3 V ...
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... These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend drive strength selection, temperature, and process. For board design CCI considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/techdocs/models/ibis.html (VOLspec (PULL-DOWN-MAX) OLspec (VCCImax – ...
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... SSTL3 (I) SSTL3 (II) Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on V considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/techdocs/models/ibis.html (PULL-DOWN-MAX (VCCImax – VOHspec (PULL-UP-MAX) Table 2-20 • ...
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Table 2-21 • I/O Short Currents I /I OSH 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Note 100° Applicable to 3.3 ...
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... The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals ...
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Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is supported as ...
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ProASIC3E DC and Switching Characteristics Test Point Datapath Figure 2-6 • AC Loading Table 2-27 • 3.3 V LVTTL / 3.3 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) 0 3.3 * Measuring ...
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Table 2-30 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: T Drive Speed Strength Grade DOUT Std. 0.66 11.01 0.04 1.20 1.57 –1 0.56 9.36 0.04 1.02 1.33 –2 0.49 ...
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ProASIC3E DC and Switching Characteristics Table 2-31 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: T Equivalent Software Default Drive Drive Strength Speed 1 Strength Option Grade t DOUT 100 µ Std. 0.66 –1 ...
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Table 2-32 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: T Equivalent Software Default Drive Drive Strength Speed 1 Strength Option Grade t DOUT 100 µ Std. 0.66 –1 0.56 –2 0.49 100 µA ...
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ProASIC3E DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2 extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table ...
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Timing Characteristics Table 2-35 • 2.5 V LVCMOS High Slew Commercial-Case Conditions: T Drive Speed Strength Grade DOUT Std. 0.66 8.82 0.04 1.51 1.66 –1 0.56 7.50 0.04 1.29 1.41 –2 0.49 6.58 0.03 ...
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ProASIC3E DC and Switching Characteristics Table 2-36 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: T Drive Speed Strength Grade t t DOUT Std. 0.66 12.00 0.04 1.51 1.66 –1 0.56 10.21 0.04 1.29 1.41 –2 0.49 ...
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V LVCMOS Low-Voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-37 • Minimum and ...
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ProASIC3E DC and Switching Characteristics Timing Characteristics Table 2-39 • 1.8 V LVCMOS High Slew Commercial-Case Conditions: T Drive Speed Strength Grade t t DOUT Std. 0.66 12.10 0.04 1.45 1.91 –1 0.56 10.30 0.04 1.23 1.62 ...
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Table 2-40 • 1.8 V LVCMOS Low Slew Commercial-Case Conditions: T Drive Speed Strength Grade DOUT Std. 0.66 15.84 0.04 1.45 1.91 –1 0.56 13.47 0.04 1.23 1.62 –2 0.49 11.83 0.03 1.08 1.42 ...
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ProASIC3E DC and Switching Characteristics 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output ...
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Timing Characteristics Table 2-43 • 1.5 V LVCMOS High Slew Commercial-Case Conditions: T Drive Speed Strength Grade DOUT Std. 0.66 8.53 0.04 1.70 2.14 –1 0.56 7.26 0.04 1.44 1.82 –2 0.49 6.37 0.03 ...
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... Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable path characterization are described VCCI for t ...
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Voltage-Referenced I/O Characteristics 3.3 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V Table 2-48 • Minimum and Maximum DC Input and Output Levels ...
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ProASIC3E DC and Switching Characteristics 2.5 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V Table 2-51 • Minimum and Maximum DC Input and ...
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V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V Table 2-54 • Minimum and Maximum DC Input and Output Levels 3.3 V ...
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ProASIC3E DC and Switching Characteristics 2.5 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V Table 2-57 • Minimum and Maximum DC Input ...
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HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-60 • Minimum and Maximum DC Input ...
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ProASIC3E DC and Switching Characteristics HSTL Class II High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-63 • ...
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SSTL2 Class I Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-66 • Minimum and Maximum DC Input and Output ...
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ProASIC3E DC and Switching Characteristics SSTL2 Class II Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-69 • Minimum and ...
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SSTL3 Class I Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-72 • Minimum and Maximum DC Input and Output ...
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ProASIC3E DC and Switching Characteristics SSTL3 Class II Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-75 • Minimum and ...
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... Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by the Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and DDR. However, there is no support for bidirectional I/Os or tristates with the LVPECL standards ...
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ProASIC3E DC and Switching Characteristics Table 2-78 • LVDS Minimum and Maximum DC Input and Output Levels DC Parameter VCCI Supply Voltage VOL Output Low Voltage VOH Output High Voltage 4 I Output Lower Current Output High ...
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... These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in ...
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ProASIC3E DC and Switching Characteristics LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. ...
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I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Preset Data D C DFN1E1P1 E Enable B CLK A Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered Figure 2-24 • Timing ...
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ProASIC3E DC and Switching Characteristics Table 2-84 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output ...
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Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear D Data CC DFN1E1C1 E Enable BB CLK AA CLR DD Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-25 • Timing Model of ...
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ProASIC3E DC and Switching Characteristics Table 2-85 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output ...
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Input Register 50% 50% CLK t ISUD 1 50% Data Enable 50% t IHE t ISUE Preset Clear Out_1 Figure 2-26 • Input Register Timing Diagram Timing Characteristics Table 2-86 • Input Data Register Propagation Delays Commercial-Case Conditions: T Parameter ...
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ProASIC3E DC and Switching Characteristics Output Register 50% CLK 1 Data_out Enable 50% t OHE t Preset OSUE Clear DOUT Figure 2-27 • Output Register Timing Diagram Timing Characteristics Table 2-87 • Output Data Register Propagation Delays Commercial-Case Conditions: T ...
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Output Enable Register 50% 50% CLK t OESUD 1 50% D_Enable 50% Enable t t OESUE OEHE Preset Clear EOUT t Figure 2-28 • Output Enable Register Timing Diagram Timing Characteristics Table 2-88 • Output Enable Register Propagation Delays Commercial-Case ...
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ProASIC3E DC and Switching Characteristics DDR Module Specifications Input DDR Module INBUF Data CLK CLKBUF CLR INBUF Figure 2-29 • Input DDR Timing Model Table 2-89 • Parameter Definitions Parameter Name t Clock-to-Out Out_QR DDRICLKQ1 t Clock-to-Out Out_QF DDRICLKQ2 t ...
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CLK Data 1 2 CLR t DDRIREMCLR t DDRICLR2Q1 Out_QF t DDRICLR2Q2 Out_QR Figure 2-30 • Input DDR Timing Diagram Timing Characteristics Table 2-90 • Input DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out Out_QR for Input DDR DDRICLKQ1 ...
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ProASIC3E DC and Switching Characteristics Output DDR Module Data_F (from core) CLK CLKBUF Data_R (from core) CLR INBUF Figure 2-31 • Output DDR Timing Model Table 2-91 • Parameter Definitions Parameter Name t Clock-to-Out DDROCLKQ t Asynchronous Clear-to-Out DDROCLR2Q t ...
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CLK Data_F DDROREMCLR Data_R CLR DDROREMCLR t DDROCLR2Q Out Figure 2-32 • Output DDR Timing Diagram Timing Characteristics Table 2-92 • Output DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out of DDR for ...
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ProASIC3E DC and Switching Characteristics VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The ProASIC3E library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer ...
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50% OUT GND t PD (RR) VCC OUT Figure 2-34 • Timing Model and Waveforms t PD NAND2 or Y Any Combinatorial Logic t = MAX PD(RR) PD(RF) where edges are ...
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ProASIC3E DC and Switching Characteristics Timing Characteristics Table 2-93 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: T Combinatorial Cell INV AND2 NAND2 OR2 NOR2 XOR2 MAJ3 XOR3 MUX2 AND3 Note: For specific junction temperature and voltage supply levels, refer to ...
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CLK t SUD 50% Data EN 50 PRE SUE CLR Out t CLKQ Figure 2-36 • Timing Model and Waveforms Timing Characteristics Table 2-94 • Register Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the ...
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ProASIC3E DC and Switching Characteristics Global Resource Characteristics A3PE600 Clock Tree Topology Clock delays are device-specific. global tree presented used to drive all D-flip-flops in the device. CCC Figure 2-37 • Example of Global Tree Use in ...
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... Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-96 • A3PE1500 Global Resource Commercial-Case Conditions: T Parameter ...
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ProASIC3E DC and Switching Characteristics Table 2-97 • A3PE3000 Global Resource Commercial-Case Conditions: T Parameter Description t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Minimum Pulse Width High for Global Clock ...
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Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-98 • ProASIC3E CCC/PLL Specification Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f Delay Increments in Programmable Delay Blocks 1 Serial Clock (SCLK) for Dynamic PLL ...
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ProASIC3E DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM Figure 2-39 • RAM Models 2- 72 RAM4K9 RADDR8 ADDRA11 DOUTA8 RADDR7 DOUTA7 ADDRA10 ADDRA0 DOUTA0 RADDR0 DINA8 DINA7 RW1 DINA0 RW0 WIDTHA1 WIDTHA0 PIPE PIPEA WMODEA BLKA REN ...
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Timing Waveforms t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-40 • RAM Read for Pass-Through Output t CKH CLK ADD 0 t ...
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ProASIC3E DC and Switching Characteristics t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-42 • RAM Write, Output Retained (WMODE = 0) CLK ADD ...
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CLK1 ADD1 DI1 CCKH CLK2 WEN_B1 WEN_B2 A ADD2 DI2 D DO2 D (pass-through) DO2 D (pipelined) Figure 2-44 • Write Access after Write onto Same Address ...
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ProASIC3E DC and Switching Characteristics CLK1 ADD1 DI1 CLK2 WEN_B1 WEN_B2 ADD2 DO2 (pass-through) DO2 (pipelined) Figure 2-45 • Read Access after Write onto Same Address ...
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CLK1 ADD1 A 0 WEN_B1 t CKQ1 DO1 D n (pass-through) DO1 D (pipelined CCKH CLK2 ADD2 A D DI2 WEN_B2 Figure 2-46 • Write Access after Read onto Same Address t CKH CLK ...
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ProASIC3E DC and Switching Characteristics Timing Characteristics Table 2-99 • RAM4K9 Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t BLK_B setup ...
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Table 2-100 • RAM512X18 Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t Input data (DI) setup time DS t Input data ...
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ProASIC3E DC and Switching Characteristics FIFO Figure 2-48 • FIFO Model 2- 80 FIFO4K18 RW2 RD17 RW1 RD16 RW0 WW2 WW1 RD0 WW0 ESTOP FULL FSTOP AFULL EMPTY AEVAL11 AEMPTY AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 ...
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Timing Waveforms RCLK/ WCLK RESET_B t RSTFG EMPTY AEMPTY t RSTFG FULL AFULL WA/RA (Address Counter) Figure 2-49 • FIFO Reset RCLK EMPTY AEMPTY WA/RA NO MATCH (Address Counter) Figure 2-50 • FIFO EMPTY Flag and AEMPTY Flag Assertion t ...
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ProASIC3E DC and Switching Characteristics WCLK FULL AFULL WA/RA NO MATCH (Address Counter) Figure 2-51 • FIFO FULL Flag and AFULL Flag Assertion WCLK MATCH WA/RA NO MATCH (Address Counter) (EMPTY) 1st Rising Edge After 1st Write RCLK EMPTY AEMPTY ...
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Timing Characteristics Table 2-101 • FIFO Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input Data (DI) Setup Time DS t ...
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ProASIC3E DC and Switching Characteristics Embedded FlashROM Characteristics t SU CLK t HOLD Address A 0 Data Figure 2-54 • Timing Diagram Timing Characteristics Table 2-102 • Embedded FlashROM Access Time Parameter t Address Setup Time SU t Address Hold ...
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... Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. ...
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...
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... Package Pin Assignments 208-Pin PQFP 208 1 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC3E Flash Family FPGAs 208-Pin PQFP ...
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Package Pin Assignments 208-Pin PQFP Pin Number A3PE600 Function 1 GND 2 GNDQ 3 VMV7 4 GAB2/IO133PSB7V1 5 GAA2/IO134PDB7V1 6 IO134NDB7V1 7 GAC2/IO132PDB7V1 8 IO132NDB7V1 9 IO130PDB7V1 10 IO130NDB7V1 11 IO127PDB7V1 12 IO127NDB7V1 13 IO126PDB7V0 14 IO126NDB7V0 15 IO124PSB7V0 16 ...
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PQFP Pin Number A3PE600 Function 108 TDO 109 TRST 110 VJTAG 111 VMV3 112 GDA0/IO67NPB3V1 113 GDB0/IO66NPB3V1 114 GDA1/IO67PPB3V1 115 GDB1/IO66PPB3V1 116 GDC0/IO65NDB3V1 117 GDC1/IO65PDB3V1 118 IO62NDB3V1 119 IO62PDB3V1 120 IO58NDB3V0 121 IO58PDB3V0 122 GND 123 VCCIB3 124 GCC2/IO55PSB3V0 ...
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... GEA2/IO166PDB5V3 57 IO165NDB5V3 58 GEB2/IO165PDB5V3 59 IO164NDB5V3 60 GEC2/IO164PDB5V3 61 IO163PSB5V3 62 VCCIB5 63 IO161PSB5V3 64 IO157NDB5V2 65 GND 66 IO157PDB5V2 67 IO153NDB5V2 68 IO153PDB5V2 69 IO149NDB5V1 70 IO149PDB5V1 71 VCC 72 VCCIB5 208-Pin PQFP Pin Number A3PE1500 Function 73 IO145NDB5V1 74 IO145PDB5V1 75 IO143NDB5V1 76 IO143PDB5V1 77 IO137NDB5V0 78 IO137PDB5V0 79 IO135NDB5V0 80 IO135PDB5V0 81 GND 82 IO131NDB4V2 83 IO131PDB4V2 84 IO129NDB4V2 85 IO129PDB4V2 86 IO127NDB4V2 87 IO127PDB4V2 88 VCC 89 VCCIB4 90 IO121NDB4V1 ...
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... IO41NDB1V1 175 IO35PDB1V0 176 IO35NDB1V0 177 IO31PDB0V3 178 GND 179 IO31NDB0V3 180 IO29PDB0V3 ProASIC3E Flash Family FPGAs 208-Pin PQFP Pin Number A3PE1500 Function 181 IO29NDB0V3 182 IO27PDB0V3 183 IO27NDB0V3 184 IO23PDB0V2 185 IO23NDB0V2 186 VCCIB0 187 VCC 188 IO18PDB0V2 189 ...
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Package Pin Assignments 208-Pin PQFP Pin Number A3PE3000 Function 1 GND 2 GNDQ 3 VMV7 4 GAB2/IO308PSB7V4 5 GAA2/IO309PDB7V4 6 IO309NDB7V4 7 GAC2/IO307PDB7V4 8 IO307NDB7V4 9 IO303PDB7V3 10 IO303NDB7V3 11 IO299PDB7V3 12 IO299NDB7V3 13 IO295PDB7V2 14 IO295NDB7V2 15 IO291PSB7V2 16 ...
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PQFP Pin Number A3PE3000 Function 118 IO134NDB3V2 119 IO134PDB3V2 120 IO132NDB3V2 121 IO132PDB3V2 122 GND 123 VCCIB3 124 GCC2/IO117PSB3V0 125 GCB2/IO116PSB3V0 126 NC 127 IO115NDB3V0 128 GCA2/IO115PDB3V0 129 GCA1/IO114PPB3V0 130 GND 131 VCCPLC 132 GCA0/IO114NPB3V0 133 VCOMPLC 134 GCB0/IO113NDB2V3 ...
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... Package Pin Assignments 256-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner ...
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FBGA Pin Number A3PE600 Function A1 GND A2 GAA0/IO00NDB0V0 A3 GAA1/IO00PDB0V0 A4 GAB0/IO01NDB0V0 A5 IO05PDB0V0 A6 IO10PDB0V1 A7 IO12PDB0V2 A8 IO16NDB0V2 A9 IO23NDB1V0 A10 IO23PDB1V0 A11 IO28NDB1V1 A12 IO28PDB1V1 A13 GBB1/IO34PDB1V1 A14 GBA0/IO35NDB1V1 A15 GBA1/IO35PDB1V1 A16 GND B1 GAB2/IO133PDB7V1 ...
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Package Pin Assignments 256-Pin FBGA Pin Number A3PE600 Function G13 GCC1/IO50PPB2V1 G14 IO44NDB2V1 G15 IO44PDB2V1 G16 IO49NSB2V1 H1 GFB0/IO119NPB7V0 H2 GFA0/IO118NDB6V1 H3 GFB1/IO119PPB7V0 H4 VCOMPLF H5 GFC0/IO120NPB7V0 H6 VCC H7 GND H8 GND H9 GND H10 GND H11 VCC H12 ...
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FBGA Pin Number A3PE600 Function P9 IO82PDB5V0 P10 IO76NDB4V1 P11 IO76PDB4V1 P12 VMV4 P13 TCK P14 VPUMP P15 TRST P16 GDA0/IO67NDB3V1 R1 GEA1/IO102PDB6V0 R2 GEA0/IO102NDB6V0 R3 GNDQ R4 GEC2/IO99PDB5V2 R5 IO95NPB5V1 R6 IO91NDB5V1 R7 IO91PDB5V1 R8 IO83NDB5V0 R9 IO83PDB5V0 ...
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... Package Pin Assignments 324-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner visio ...
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FBGA Pin Number A3PE3000 FBGA A1 GND A2 IO08NDB0V0 A3 IO08PDB0V0 A4 IO10NDB0V1 A5 IO10PDB0V1 A6 IO12PDB0V1 A7 GND A8 IO32NDB0V3 A9 IO32PDB0V3 A10 IO42PPB1V0 A11 IO52NPB1V1 A12 GND A13 IO66NDB1V3 A14 IO72NDB1V3 A15 IO72PDB1V3 A16 IO74NDB1V4 A17 IO74PDB1V4 ...
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Package Pin Assignments 324-Pin FBGA Pin Number A3PE3000 FBGA G1 GND G2 IO287PDB7V1 G3 IO287NDB7V1 G4 IO283PPB7V1 G5 VCCIB7 G6 IO279PDB7V0 G7 IO291NPB7V2 G8 VCC G9 IO26NDB0V3 G10 IO34NDB0V4 G11 VCC G12 IO94NPB2V1 G13 IO98PDB2V2 G14 VCCIB2 G15 GCC0/IO112NPB2V3 G16 ...
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FBGA Pin Number A3PE3000 FBGA N1 IO247NDB6V1 N2 IO247PDB6V1 N3 IO251NPB6V2 N4 GEC0/IO236NDB6V0 N5 VCOMPLE N6 IO212NDB5V2 N7 IO212PDB5V2 N8 IO192NPB4V4 N9 IO174PDB4V2 N10 IO170PDB4V2 N11 GDA2/IO154PPB4V0 N12 GDB2/IO155PPB4V0 N13 GDA1/IO153PPB3V4 N14 VCOMPLD N15 GDB0/IO152NDB3V4 N16 GDB1/IO152PDB3V4 N17 IO138NDB3V3 ...
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... Package Pin Assignments 484-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner visio ...
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FBGA Pin Number A3PE600 Function A1 GND A2 GND A3 VCCIB0 A4 IO06NDB0V1 A5 IO06PDB0V1 A6 IO08NDB0V1 A7 IO08PDB0V1 A8 IO11PDB0V1 A9 IO17PDB0V2 A10 IO18NDB0V2 A11 IO18PDB0V2 A12 IO22PDB1V0 A13 IO26PDB1V0 A14 IO29NDB1V1 A15 IO29PDB1V1 A16 IO31NDB1V1 A17 IO31PDB1V1 ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3PE600 Function C21 NC C22 VCCIB2 GND D5 GAA0/IO00NDB0V0 D6 GAA1/IO00PDB0V0 D7 GAB0/IO01NDB0V0 D8 IO05PDB0V0 D9 IO10PDB0V1 D10 IO12PDB0V2 D11 IO16NDB0V2 D12 IO23NDB1V0 D13 IO23PDB1V0 D14 ...
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FBGA Pin Number A3PE600 Function H19 IO41PDB2V0 H20 VCC H21 NC H22 NC J1 IO123NDB7V0 J2 IO123PDB7V0 IO124PDB7V0 J5 IO125PDB7V0 J6 IO126PDB7V0 J7 IO130NDB7V1 J8 VCCIB7 J9 GND J10 VCC J11 VCC J12 VCC J13 VCC ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3PE600 Function N17 IO57NPB3V0 N18 IO55NPB3V0 N19 IO57PPB3V0 N20 NC N21 IO56NDB3V0 N22 IO58PDB3V0 IO111PDB6V1 P3 IO115NPB6V1 P4 IO113NPB6V1 P5 IO109PPB6V0 P6 IO108PDB6V0 P7 IO108NDB6V0 P8 VCCIB6 P9 GND P10 ...
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FBGA Pin Number A3PE600 Function V15 IO69NDB4V0 V16 GDB2/IO69PDB4V0 V17 TDI V18 GNDQ V19 TDO V20 GND V21 NC V22 IO63NDB3V1 GND W5 IO100NDB5V2 W6 GEB2/IO100PDB5V2 W7 IO99NDB5V2 W8 IO88NDB5V0 W9 IO88PDB5V0 ...
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... AB18 NC AB19 NC AB20 VCCIB4 AB21 GND AB22 GND B1 GND B2 VCCIB7 IO03NDB0V0 B5 IO03PDB0V0 B6 IO10NDB0V1 R e visio n 9 484-Pin FBGA Pin Number A3PE1500 Function B7 IO10PDB0V1 B8 IO15NDB0V1 B9 IO17NDB0V2 B10 IO20PDB0V2 B11 IO29PDB0V3 B12 IO32NDB1V0 B13 IO43NDB1V1 B14 NC B15 NC B16 IO53NDB1V2 B17 IO53PDB1V2 B18 IO54PDB1V3 ...
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... F17 VMV2 F18 IO58NDB2V0 F19 IO63PDB2V0 F20 NC F21 NC F22 NC G1 IO211NDB7V2 G2 IO211PDB7V2 IO214PDB7V3 ProASIC3E Flash Family FPGAs 484-Pin FBGA Pin Number A3PE1500 Function G5 IO217PDB7V3 G6 GAC2/IO219PDB7V3 G7 VCOMPLA G8 GNDQ G9 IO19NDB0V2 G10 IO19PDB0V2 G11 IO25PDB0V3 G12 IO33PDB1V0 G13 IO39PDB1V0 G14 IO45NDB1V1 G15 GNDQ G16 ...
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... L15 GCC0/IO85NPB2V3 L16 GCB1/IO86PPB2V3 L17 GCA0/IO87NPB3V0 L18 VCOMPLC L19 GCB0/IO86NPB2V3 L20 IO81PPB2V3 L21 IO83NDB2V3 L22 IO83PDB2V3 M1 GNDQ M2 IO185NPB6V2 R e visio n 9 484-Pin FBGA Pin Number A3PE1500 Function M3 IO189NDB6V2 M4 GFA2/IO189PDB6V2 M5 GFA1/IO190PDB6V2 M6 VCCPLF M7 IO188NDB6V2 M8 GFB2/IO188PDB6V2 M9 VCC M10 GND M11 GND M12 GND M13 ...
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... IO119NDB4V1 T14 IO119PDB4V1 T15 GNDQ T16 VCOMPLD T17 VJTAG T18 GDC0/IO108NDB3V2 T19 GDA1/IO110PDB3V2 T20 NC T21 IO103PDB3V2 T22 IO101NDB3V1 ProASIC3E Flash Family FPGAs 484-Pin FBGA Pin Number A3PE1500 Function U1 IO175PPB6V1 U2 IO173PDB6V0 U3 IO173NDB6V0 U4 GEB1/IO168PDB6V0 U5 GEB0/IO168NDB6V0 U6 VMV6 U7 VCCPLE U8 IO166NPB5V3 U9 IO157PPB5V2 U10 IO145PDB5V1 U11 IO141PDB5V0 ...
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... IO111NDB4V0 W17 GDA2/IO111PDB4V0 W18 TMS W19 GND W20 NC W21 NC W22 NC Y1 VCCIB6 IO161NDB5V3 Y5 GND Y6 IO163NDB5V3 3- 26 484-Pin FBGA Pin Number A3PE1500 Function Y7 IO163PDB5V3 Y8 VCC Y9 VCC Y10 IO147PDB5V1 Y11 IO133PDB4V2 Y12 IO131NPB4V2 Y13 NC Y14 VCC Y15 VCC Y16 NC Y17 NC Y18 GND Y19 NC ...
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FBGA Pin Number A3PE3000 Function A1 GND A2 GND A3 VCCIB0 A4 IO10NDB0V1 A5 IO10PDB0V1 A6 IO16NDB0V1 A7 IO16PDB0V1 A8 IO18PDB0V2 A9 IO24PDB0V2 A10 IO28NDB0V3 A11 IO28PDB0V3 A12 IO46PDB1V0 A13 IO54PDB1V1 A14 IO56NDB1V1 A15 IO56PDB1V1 A16 IO64NDB1V2 A17 IO64PDB1V2 ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3PE3000 Function C21 IO94PPB2V1 C22 VCCIB2 D1 IO293PDB7V2 D2 IO303NDB7V3 D3 IO305NDB7V3 D4 GND D5 GAA0/IO00NDB0V0 D6 GAA1/IO00PDB0V0 D7 GAB0/IO01NDB0V0 D8 IO20PDB0V2 D9 IO22PDB0V2 D10 IO30PDB0V3 D11 IO38NDB0V4 D12 IO52NDB1V1 D13 IO52PDB1V1 D14 ...
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FBGA Pin Number A3PE3000 Function H19 IO100PDB2V2 H20 VCC H21 VMV2 H22 IO105PDB2V2 J1 IO285NDB7V1 J2 IO285PDB7V1 J3 VMV7 J4 IO279PDB7V0 J5 IO283PDB7V1 J6 IO281PDB7V0 J7 IO287NDB7V1 J8 VCCIB7 J9 GND J10 VCC J11 VCC J12 VCC J13 VCC ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3PE3000 Function N17 IO132NPB3V2 N18 IO117NPB3V0 N19 IO132PPB3V2 N20 GNDQ N21 IO126NDB3V1 N22 IO128PDB3V1 P1 IO247PDB6V1 P2 IO253PDB6V2 P3 IO270NPB6V4 P4 IO261NPB6V3 P5 IO249PPB6V1 P6 IO259PDB6V3 P7 IO259NDB6V3 P8 VCCIB6 P9 GND P10 ...
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FBGA Pin Number A3PE3000 Function V15 IO155NDB4V0 V16 GDB2/IO155PDB4V0 V17 TDI V18 GNDQ V19 TDO V20 GND V21 IO146PDB3V4 V22 IO142NDB3V3 W1 IO239NDB6V0 W2 IO237PDB6V0 W3 IO230PSB5V4 W4 GND W5 IO232NDB5V4 W6 GEB2/IO232PDB5V4 W7 IO231NDB5V4 W8 IO214NDB5V2 W9 IO214PDB5V2 ...
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... Package Pin Assignments 676-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx visio Ball Pad Corner ...
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... AB14 IO135PDB5V0 AB15 IO132PDB4V2 AB16 IO129PDB4V2 AB17 IO121PDB4V1 AB18 IO119NDB4V1 AB19 IO112NDB4V0 AB20 VMV4 ProASIC3E Flash Family FPGAs 676-Pin FBGA Pin Number A3PE1500 Function AB21 TCK AB22 TRST AB23 GDC0/IO108NDB3V2 AB24 GDC1/IO108PDB3V2 AB25 IO104NDB3V2 AB26 IO104PDB3V2 AC1 IO170PDB6V0 AC2 GEB0/IO168NPB6V0 AC3 ...
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... AF15 IO136PDB5V0 AF16 IO131NDB4V2 AF17 IO131PDB4V2 AF18 IO128NDB4V2 AF19 IO128PDB4V2 AF20 IO122NDB4V1 AF21 IO122PDB4V1 AF22 IO116NDB4V0 AF23 IO113NDB4V0 AF24 IO111NDB4V0 R e visio n 9 676-Pin FBGA Pin Number A3PE1500 Function AF25 GND AF26 GND B1 GND B2 GND B3 GND B4 GND B5 IO06PDB0V0 B6 IO04NDB0V0 B7 IO07NDB0V0 B8 IO11NDB0V1 B9 ...
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... IO54NDB1V3 E20 IO52NDB1V2 E21 IO52PDB1V2 E22 VCCPLB E23 GBA1/IO57PPB1V3 E24 IO63PDB2V0 E25 IO63NDB2V0 E26 IO68PDB2V1 F1 IO212NDB7V2 F2 IO203PPB7V1 ProASIC3E Flash Family FPGAs 676-Pin FBGA Pin Number A3PE1500 Function F3 IO213NDB7V2 F4 IO213PDB7V2 F5 GND F6 VCCPLA F7 GAB0/IO01NDB0V0 F8 GNDQ F9 IO03PDB0V0 F10 IO13PDB0V1 F11 IO15PDB0V1 F12 IO19PDB0V2 F13 ...
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... J23 IO69NDB2V1 J24 VMV2 J25 IO80PDB2V3 J26 IO80NDB2V3 K1 IO195PDB7V0 K2 IO199NDB7V1 K3 IO199PDB7V1 K4 IO205NDB7V1 K5 IO205PDB7V1 K6 IO217PDB7V3 R e visio n 9 676-Pin FBGA Pin Number A3PE1500 Function K7 IO217NDB7V3 K8 VCCIB7 K9 VCC K10 GND K11 GND K12 GND K13 GND K14 GND K15 GND K16 GND K17 ...
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... P2 VCCPLF P3 IO193PPB7V0 P4 IO196NDB7V0 P5 GFA1/IO190PDB6V2 P6 IO194PDB7V0 P7 IO194NDB7V0 P8 VCCIB6 P9 VCC P10 GND ProASIC3E Flash Family FPGAs 676-Pin FBGA Pin Number A3PE1500 Function P11 GND P12 GND P13 GND P14 GND P15 GND P16 GND P17 GND P18 VCC P19 VCCIB3 P20 GCC0/IO85NDB2V3 P21 ...
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... IO176PDB6V1 V7 IO176NDB6V1 V8 VCCIB6 V9 VCC V10 VCC V11 VCC V12 VCC V13 VCC V14 VCC R e visio n 9 676-Pin FBGA Pin Number A3PE1500 Function V15 VCC V16 VCC V17 VCC V18 VCC V19 VCCIB3 V20 IO107PDB3V2 V21 IO107NDB3V2 V22 IO103NDB3V2 V23 IO103PDB3V2 ...
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... FBGA Pin Number A3PE1500 Function W25 IO96PDB3V1 W26 IO94NDB3V0 Y1 IO175NDB6V1 Y2 IO175PDB6V1 Y3 IO173NDB6V0 Y4 IO173PDB6V0 Y5 GEC1/IO169PPB6V0 Y6 GNDQ Y7 VMV6 Y8 VCCIB5 Y9 IO163NDB5V3 Y10 IO159PDB5V3 Y11 IO153PDB5V2 Y12 IO147PDB5V1 Y13 IO139PDB5V0 Y14 IO137PDB5V0 Y15 IO125NDB4V1 Y16 IO125PDB4V1 Y17 IO115NDB4V0 Y18 IO115PDB4V0 Y19 VCC Y20 VPUMP ...
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... Package Pin Assignments 896-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx visio Ball Pad Corner ...
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FBGA Pin Number A3PE3000 Function A2 GND A3 GND A4 IO14NPB0V1 A5 GND A6 IO07NPB0V0 A7 GND A8 IO09NDB0V1 A9 IO17NDB0V2 A10 IO17PDB0V2 A11 IO21NDB0V2 A12 IO21PDB0V2 A13 IO33NDB0V4 A14 IO33PDB0V4 A15 IO35NDB0V4 A16 IO35PDB0V4 A17 IO41NDB1V0 A18 IO43NDB1V0 ...
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Package Pin Assignments 896-Pin FBGA Pin Number A3PE3000 Function AC21 IO164PDB4V1 AC22 IO162PPB4V1 AC23 GND AC24 VCOMPLD AC25 IO150NDB3V4 AC26 IO148NDB3V4 AC27 GDA1/IO153PDB3V4 AC28 IO145NDB3V3 AC29 IO143NDB3V3 AC30 IO137NDB3V2 AD1 GND AD2 IO242NPB6V1 AD3 IO240NDB6V0 AD4 GEC0/IO236NDB6V0 AD5 VCCIB6 AD6 ...
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FBGA Pin Number A3PE3000 Function AG9 IO225NPB5V3 AG10 IO223NPB5V3 AG11 IO221PDB5V3 AG12 IO221NDB5V3 AG13 IO205NPB5V1 AG14 IO199NDB5V0 AG15 IO199PDB5V0 AG16 IO187NDB4V4 AG17 IO187PDB4V4 AG18 IO181NDB4V3 AG19 IO171PPB4V2 AG20 IO165NPB4V1 AG21 IO161NPB4V0 AG22 IO159NDB4V0 AG23 IO159PDB4V0 AG24 IO158PPB4V0 AG25 GDB2/IO155PDB4V0 ...
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Package Pin Assignments 896-Pin FBGA Pin Number A3PE3000 Function AK28 GND AK29 GND B1 GND B2 GND B3 GAA2/IO309PPB7V4 B4 VCC B5 IO14PPB0V1 B6 VCC B7 IO07PPB0V0 B8 IO09PDB0V1 B9 IO15PPB0V1 B10 IO19NDB0V2 B11 IO19PDB0V2 B12 IO29NDB0V3 B13 IO29PDB0V3 B14 ...
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FBGA Pin Number A3PE3000 Function E17 IO49PDB1V1 E18 IO50PDB1V1 E19 IO58PDB1V2 E20 IO60NDB1V2 E21 IO77PDB1V4 E22 IO68NDB1V3 E23 IO68PDB1V3 E24 VCCIB1 E25 IO74PDB1V4 E26 VCC E27 GBB1/IO80PPB1V4 E28 VCCIB2 E29 IO82NPB2V0 E30 GND F1 IO296PPB7V2 F2 VCC F3 IO306PDB7V4 ...
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Package Pin Assignments 896-Pin FBGA Pin Number A3PE3000 Function J5 IO295NDB7V2 J6 IO299NDB7V3 J7 VCCIB7 J8 VCCPLA J9 VCC J10 IO04NPB0V0 J11 IO18NDB0V2 J12 IO20NDB0V2 J13 IO20PDB0V2 J14 IO32NDB0V3 J15 IO32PDB0V3 J16 IO42PDB1V0 J17 IO44NDB1V0 J18 IO44PDB1V0 J19 IO54NDB1V1 J20 ...
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FBGA Pin Number A3PE3000 Function M23 IO104PPB2V2 M24 IO102PDB2V2 M25 IO102NDB2V2 M26 IO95PDB2V1 M27 IO97NDB2V1 M28 IO101NDB2V2 M29 IO103NDB2V2 M30 IO119PDB3V0 N1 IO276PDB7V0 N2 IO278PDB7V0 N3 IO280PDB7V0 N4 IO284PDB7V1 N5 IO279PDB7V0 N6 IO285NDB7V1 N7 IO287NDB7V1 N8 IO281NDB7V0 N9 IO281PDB7V0 ...
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Package Pin Assignments 896-Pin FBGA Pin Number A3PE3000 Function T11 VCC T12 GND T13 GND T14 GND T15 GND T16 GND T17 GND T18 GND T19 GND T20 VCC T21 VCCIB3 T22 IO109NPB2V3 T23 IO116NDB3V0 T24 IO118NDB3V0 T25 IO122NPB3V1 T26 ...
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FBGA Pin Number A3PE3000 Function W29 IO131PDB3V2 W30 IO123NDB3V1 Y1 IO266PDB6V4 Y2 IO250PDB6V2 Y3 IO250NDB6V2 Y4 IO246PDB6V1 Y5 IO247NDB6V1 Y6 IO247PDB6V1 Y7 IO249NPB6V1 Y8 IO245PDB6V1 Y9 IO253NDB6V2 Y10 GEB0/IO235NPB6V0 Y11 VCC Y12 VCC Y13 VCC Y14 VCC Y15 VCC ...
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...
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Datasheet Information List of Changes The following table lists critical changes that were made in each revision of the ProASIC3E datasheet. Revision July 2010 The versioning system for datasheets has been changed. Datasheets are assigned a revision number ...
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Datasheet Information Revision Revision 5 (Jun 2008) The naming conventions changed for the following pins in the the A3PE600: Packaging v1.4 Pin Number J19 K20 Revision 4 (Apr 2008) The product brief portion of the datasheet ...
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... FBGA" The "896-Pin FBGA" Revision 0 (Jan 2008) This document was previously in datasheet v2. result of moving to the handbook format, Actel has restarted the version numbers. The new version number is 51700098-001-0. v2.1 CoreMP7 information was removed from the "Features and Benefits" section. (July 2007) The M1 device part numbers have been updated in Table 4 • ...
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... The A3PE1500 "208-Pin PQFP" table is new. The A3PE1500 "484-Pin FBGA" table is new. The A3PE1500 "A3PE1500 Function" table is new. Advance v0.6 In the "Packaging Tables" table, the number of I/Os for the A3PE1500 was (January 2007) changed for the FG484 and FG676 packages. Advance v0.5 B-LVDS and M-LDVS are new I/O standards added to the datasheet ...
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Revision Advance v0.5 The "WCLK and RCLK" section was updated. (continued) The "RESET" section was updated. The "RESET" section was updated. B-LVDS and M-LDVS are new I/O standards added to the datasheet. The term flow-through was changed to pass-through. Figure ...
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Datasheet Information Revision Advance v0.5 The CCC Output Peak-to-Peak Period Jitter F (continued) 2-13 • ProASIC3E CCC/PLL Specification. EXTFB was removed from Figure 2-27 • CCC/PLL Macro. The LVPECL specification in Table 2-45 • I/O Hot-Swap and 5 V Input ...
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Revision Advance v0.3 Table 2-5 was updated. (continued) Table 2-6 was updated. The "FIFO Flag Usage Considerations" section was updated. Table 2-33 was updated. Figure 2-24 was updated. The "Cold-Sparing Support" section is new. Table 2-45 was updated. Table 2-48 ...
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... Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. ...
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...
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... Fax +44 (0) 1276 607 540 © Actel Corporation. All rights reserved. Actel, Actel Fusion, IGLOO, Libero, Pigeon Point, ProASIC, SmartFusion and the associated logos are trademarks or registered trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners. Actel Japan ...