MAX1473EUI+ Maxim Integrated Products, MAX1473EUI+ Datasheet - Page 12

• Manufacturer Part Number: MAX1473EUI+
• Description: RF Receiver IC RCVR 315/433MHZ ASK
• Manufacturer: Maxim Integrated Products
• Type: 315 MHz or 433 MHz Superheterodyne Receiverr

Specifications of MAX1473EUI+

• Operating Frequency: 315 MHz, 433 MHz
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 5.2 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Package / Case: TSSOP-28, QFN-32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Figure 2. Generating Data Slicer Threshold
Note that a long string of zeros or 1’s can cause the
threshold to drift. This configuration works best if a cod-
ing scheme, such as Manchester coding, which has an
equal number of zeros and 1’s, is used.
To prevent continuous toggling of DATAOUT in the
absence of an RF signal due to noise, hysteresis can
be added to the data slicer as shown in Figure 3.
The peak detector output (PDOUT), in conjunction with
an external RC filter, creates a DC output voltage equal
to the peak value of the data signal. The resistor pro-
vides a path for the capacitor to discharge, allowing the
peak detector to dynamically follow peak changes of
the data filter output voltage. For faster receiver startup,
the circuit shown in Figure 4 can be used.
A properly designed PCB is an essential part of any
RF/microwave circuit. On high-frequency inputs and
outputs, use controlled-impedance lines and keep
them as short as possible to minimize losses and radia-
tion. At high frequencies, trace lengths that are on the
order of λ/10 or longer act as antennas.
Keeping the traces short also reduces parasitic induc-
tance. Generally, 1in of a PCB trace adds about 20nH
of parasitic inductance. The parasitic inductance can
have a dramatic effect on the effective inductance of a
passive component. For example, a 0.5in trace con-
necting a 100nH inductor adds an extra 10nH of induc-
tance or 10%.
To reduce the parasitic inductance, use wider traces
and a solid ground or power plane below the signal
traces. Also, use low-inductance connections to ground
on all GND pins, and place decoupling capacitors
close to all power-supply pins.
12
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25
DATAOUT
C4
DATA
SLICER
20
DSN
Layout Considerations
R1
MAX1473
DSP
23
Peak Detector
19
DFO
PROCESS: CMOS
Figure 3. Generating Data Slicer Hysteresis
Figure 4. Using PDOUT for Faster Startup
R1
R2
25
DATAOUT
*OPTIONAL
25
DATAOUT
47nF
DSN
DATA
SLICER
DATA
SLICER
DSP
20
MAX1473
23
25kΩ
R3
DSP
Chip Information
23
C4
DSN
20
19
DFO
MAX1473
R4
PDOUT
19
DFO
26