NTE859 NTE ELECTRONICS, NTE859 Datasheet

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NTE859

Manufacturer Part Number
NTE859
Description
Replacement Semiconductors DIP-14 QUAD OP AMP
Manufacturer
NTE ELECTRONICS
Datasheet

Specifications of NTE859

Op Amp Type
Low Noise
No. Of Amplifiers
4
Bandwidth
3MHz
Slew Rate
13V/µs
Supply Voltage Range
± 15V
Amplifier Case Style
DIP
No. Of Pins
14
Operating Temperature Range
0°C To +70°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Description:
The NTE859 (14−Lead DIP) and NTE859SM (SOIC−14 Surface Mount) JFET−input operational am-
plifiers are low noise amplifiers with low noise input bias, offset currents, and fast slew rate. The low
harmonic distortion and low noise make these devices ideally suited as amplifiers for high−fidelity and
audio preamplifier applications. Each amplifier features JFET−inputs (for high input impedance)
coupled with bipolar output stages all integrated on a single monolithic chip.
Features:
D Low Power Consumption
D Wide Common−Mode and Differential Voltage Ranges
D Low Input Bias and Offset Currents
D Output Short−Circuit Protection
D Low Total Harmonic Distortion: 0.003% Typ
D Low Noise: Vn = 18nV H
D High Input Impedance: JFET−Input Stage
D Internal Frequency Compensation
D Latch−Up Free Operation
D High Slew Rate: 13V/ s Typ
Absolute Maximum Ratings: (T
Supply Voltage (Note 1), V
Supply Voltage (Note1), V
Differential Input Voltage (Note 2), V
Input Voltage Range (Note 1, Note 3),V
Duration of Output Short Circuit (Note 4),t
Power Dissipation (T
Operating Ambient Temperature Range, T
Storage Temperature Range, T
Lead Temperature (During Soldering, 1/16” from Case for 10sec), T
Note 1. All voltage values, except differential voltages, are with reapect to the midpoint between
Note 2. Differential voltages are at the non−inverting input pin with respect to the inverting pin.
Note 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage
Note 4. The output may be shorted to GND or to either supply. Temperature and/or supply voltages
Derate Above 25 C
V
or 15V, whichever is less.
must be limited to ensure that the dissipation rating is not exceeded.
CC
(+) and V
A
CC
= +25 C), P
(−).
CC
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quad, Low Noise, JFET Input
(−)
(+)
Z
stg
Typ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
Operational Amplifier
D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NTE859/NTE859SM
= 0 to +70 C unless otherwise specified)
ID
Integrated Circuit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDR
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
L
. . . . . . . . . . . . . . . . . .
−65 to +150 C
0 to +70 C
10mW/ C
Unlimited
680mW
+260 C
−18V
18V
30V
15V

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NTE859 Summary of contents

Page 1

... Description: The NTE859 (14−Lead DIP) and NTE859SM (SOIC−14 Surface Mount) JFET−input operational am- plifiers are low noise amplifiers with low noise input bias, offset currents, and fast slew rate. The low harmonic distortion and low noise make these devices ideally suited as amplifiers for high−fidelity and audio preamplifier applications. Each amplifier features JFET− ...

Page 2

Electrical Characteristics: (V Parameter Input Offset Voltage Temperature Coefficient of Input Offset Voltage Input Offset Current Input Bias Current Common−Mode Input Voltage Range Maximum Peak Output Voltage Range Large−Signal Differential Voltage Amplification Unity−Gain Bandwidth Input Resistance Common−Mode Rejection Ratio SupplyVoltage ...

Page 3

... Pin Connection Diagram Output 1 1 Invert Input 1 2 Non−Invert Input (+) 4 CC Non−Invert Input 2 5 Invert Input 2 6 Output 2 7 NTE859 (14−Lead DIP .785 (19.95) Max .100 (2.45) .600 (15.24) NTE859SM (SOIC−14) .340 (8.64 .050 (1.27) 14 Output 3 13 Invert Input 3 12 Non− ...

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