LIS331DL STMicroelectronics, LIS331DL Datasheet
LIS331DL
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LIS331DL Summary of contents
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... Motion activated functions ■ Gaming and virtual reality input devices ■ Vibration monitoring and compensation Description The LIS331DL, belonging to the “nano” family of ST motion sensors, is the smallest consumer low- power three axes linear accelerometer. The 2 device features digital I C/SPI serial interface standard output and smart embedded functions ...
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... I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.1 5.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.1 5.2.2 5.2.3 2/42 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Click and double click recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 LIS331DL ...
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... LIS331DL 6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 WHO_AM_I (0Fh 7.2 CTRL_REG1 (20h 7.3 CTRL_REG2 (21h 7.4 CTRL_REG3 [interrupt CTRL register] (22h 7.5 HP_FILTER_RESET (23h 7.6 STATUS_REG (27h 7.7 OUT_X (29h 7.8 OUT_Y (2Bh 7.9 OUT_Z (2Dh 7.10 FF_WU_CFG_1 (30h 7.11 FF_WU_SRC_1 (31h ...
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... Contents 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4/42 LIS331DL ...
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... Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. SPI slave timing diagram (2 Figure 4. I2C slave timing diagram ( Figure 5. LIS331DL electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. Read & write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. Multiple bytes SPI read protocol (2 bytes example Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 10 ...
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... FF_WU_DURATION_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 37. FF_WU_DURATION_1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 38. FF_WU_CFG_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 39. FF_WU_CFG_2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 40. FF_WU_SRC_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 41. FF_WU_SRC_2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 42. FF_WU_THS_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 43. FF_WU_THS_2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 44. FF_WU_DURATION_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 45. FF_WU_DURATION_2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 46. CLICK_CFG register Table 47. CLICK_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 48. Click interrupt configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6/42 LIS331DL ...
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... LIS331DL Table 49. CLICK_SRC register Table 50. CLICK_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 51. CLICK_THSY_X register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 52. CLICK_THSY_X description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 53. CLICK_THSZ register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 54. CLICK_THSZ description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 55. CLICK_TimeLimit register Table 56. CLICK_Latency Table 57. CLICK_Window register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 58. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 List of tables 7/42 ...
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... Pin description Figure 2. Pin connection X Y DIRECTION OF THE DETECTABLE ACCELERATIONS 8/ CHARGE AMPLIFIER Z+ A/D MUX CONVERTER TRIMMING REFERENCE CIRCUITS Z 1 (TOP VIEW) LIS331DL CS 2 SCL/SPC I C CONTROL LOGIC SDA/SDO/SDI SPI SDO CONTROL LOGIC CLOCK & INTERRUPT GEN (BOTTOM VIEW) INT 1 INT 2 ...
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... LIS331DL Table 2. Pin description Pin Name Vdd_IO Power supply for I/O pins NC Internally Not Connected NC Internally Not Connected 2 SCL I C Serial Clock (SCL) SPC SPI Serial Port Clock (SPC) GND 0V supply 2 SDA I C Serial Data (SDA) SDI SPI Serial Data Input (SDI) ...
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... Best fit straight line FS bit set to 0 STP bit used X axis FS bit set to 0 STP bit used Y axis FS bit set to 0 STP bit used Z axis . 1LSb=4.6g/256 at 8bit representation, ±2.3 g Full-Scale Table 4 for specifications LIS331DL (1) (2) Min. Typ. Max. Unit ±2.0 ±2.3 ±8.0 ±9.2 16 ...
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... LIS331DL 2.2 Electrical characteristics Table 4. Electrical characteristics @ Vdd=2 °C unless otherwise noted Symbol Parameter Vdd Supply voltage Vdd_IO I/O pins supply voltage Idd Supply current Current consumption in IddPdn power-down mode VIH Digital high level input voltage VIL Digital low level input voltage ...
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... Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and Output port 3. When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors 12/42 Parameter (2) t c(SPC) t h(SI) MSB v(SO) h(SO) MSB OUT LIS331DL (1) Value Unit Min Max 100 ns 10 MHz ...
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... LIS331DL 2 2.3 Inter IC control interface Subject to general operating conditions for Vdd and top. 2 Table slave timing values Symbol Parameter f SCL clock frequency (SCL) t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time ...
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... Supply voltage on any pin should never exceed 6.0 V This is a mechanical shock sensitive device, improper handling can cause permanent damages to the part This is an ESD sensitive device, improper handling can cause permanent damages to the part 14/42 Ratings LIS331DL Maximum value Unit -0 -0 ...
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... LIS331DL 2.5 Terminology 2.5.1 Sensitivity Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ± ...
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... The acceleration data may be accessed through an I device particularly suitable for direct interfacing with a microcontroller. The LIS331DL features a Data-Ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device. ...
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... LIS331DL 4 Application hints Figure 5. LIS331DL electrical connection Vdd The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Al) should be placed as near as possible to the pin 14 of the device (common design practice). ...
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... DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor embedded inside the LIS331DL. When the bus is free both the lines are high. 2 The I C interface is compliant with fast mode (400 kHz) I normal mode ...
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... If they match, the device considers itself addressed by the Master. The Slave ADdress (SAD) associated to the LIS331DL is 001110xb. SDO/SA0 pad can be used to modify less significant bit of the device address. If SDO pad is connected to voltage supply LSb is ‘1’ (address 0011101b) else if SDO pad is connected to ground LSb value is ‘ ...
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... In the presented communication format MAK is Master Acknowledge and NMAK is No Master Acknowledge. 5.2 SPI bus interface The LIS331DL SPI is a bus slave. The SPI allows to write and read the registers of the device. The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. Figure 6. ...
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... LIS331DL Both the Read Register and Write Register commands are completed in 16 clock pulses or in multiple case of multiple bytes read/write. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...
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... AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 AD5 AD4 AD3 AD2 AD1 AD0 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 LIS331DL ...
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... LIS331DL 5.2.3 SPI read in 3-wires mode 3-wires mode is entered by setting to 1 bit SIM (SPI Serial Interface Mode selection) in CTRL_REG2. Figure 11. SPI read protocol in 3-wires mode CS SPC SDI/O The SPI Read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. ...
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... LIS331DL Comment Reserved Dummy register Reserved Dummy register Reserved Not Used Not Used Not Used Reserved Not Used ...
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... LIS331DL Table 15. Register address map (continued) Name CLICK_THSZ CLICK_TimeLimit CLICK_Latency CLICK_Window Registers marked as “Reserved” must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values ...
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... The registers address, made of 7 bits, is used to identify them and to write the data through serial interface. 7.1 WHO_AM_I (0Fh) Table 16. WHO_AM_I register 0 0 Device identification register. This register contains the device identifier that for LIS331DL is set to 3Bh. 7.2 CTRL_REG1 (20h) Table 17. CTRL_REG1 register DR PD Table 18. CTRL_REG1 description DR Data rate selection ...
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... LIS331DL Zen bit enables the generation of Data Ready signal for Z-axis measurement channel when set to 1. The default value is 1. Yen bit enables the generation of Data Ready signal for Y-axis measurement channel when set to 1. The default value is 1. Xen bit enables the generation of Data Ready signal for X-axis measurement channel when set to 1 ...
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... If the high pass filter is enabled all three axes are instantaneously set This allows to overcome the settling time of the high pass filter. 28/42 ft (Hz) (ODR=100 Hz 0.5 0.25 I2_CFG2 I2_CFG1 I2_CFG0 I1(2)_CFG1 I1(2)_CFG0 LIS331DL ft (Hz) (ODR=400 Hz I1_CFG2 I1_CFG1 I1_CFG0 INT 1(2) Pad GND FF_WU_1 FF_WU_2 FF_WU_1 OR FF_WU_2 Data ready Click interrupt ...
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... LIS331DL 7.6 STATUS_REG (27h) Table 25. STATUS_REG register ZYXOR ZOR Table 26. STATUS_REG description axis Data Overrun. Default value: 0 ZYXOR (0: no overrun has occurred; 1: new data has overwritten the previous one before it was read) Z axis Data Overrun. Default value: 0 ZOR (0: no overrun has occurred; ...
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... Enable interrupt generation on X Low event. Default value: 0 XLIE (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) 30/42 ZD5 ZD4 ZD3 ZHIE ZLIE YHIE LIS331DL ZD2 ZD1 ZD0 YLIE XHIE XLIE ...
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... LIS331DL 7.11 FF_WU_SRC_1 (31h) Table 32. FF_WU_SRC_1 register -- IA Table 33. FF_WU_SRC_1 description Interrupt Active. Default value (0: no interrupt has been generated; 1: one or more interrupts have been generated) Z High. Default value (0: no interrupt High event has occurred) Z Low. Default value (0: no interrupt Low event has occurred) Y High ...
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... XLIE Enable interrupt generation on X Low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) 32/ Duration value. Default value: 0000 0000 ZHIE ZLIE YHIE YLIE XHIE LIS331DL D0 XLIE ...
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... LIS331DL 7.15 FF_WU_SRC_2 (35h) Table 40. FF_WU_SRC_2 register -- IA Table 41. FF_WU_SRC_2 description IA Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated High. Default value: 0 (0: no interrupt High event has occurred Low. Default value: 0 (0: no interrupt Low event has occurred High ...
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... Enable interrupt generation on double click event on X axis. Default value: 0 (0: disable interrupt request; 1: enable interrupt request) Enable interrupt generation on single click event on X axis. Default value: 0 (0: disable interrupt request; 1: enable interrupt request Double_Y Single_Y Double_X LIS331DL D0 Single_X ...
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... LIS331DL Table 48. Click interrupt configurations Double_Z / 7.19 CLICK_SRC (39h) Table 49. CLICK_SRC register -- IA Table 50. CLICK_SRC description IA Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) Double_Z Double click on Z axis event. Default value: 0 (0: no interrupt; 1: Double Z event has occurred) Single_Z Single click on Z axis event ...
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... From 0 to 255 msec with step of 1 msec. 7.24 CLICK_Window (3Fh) Table 57. CLICK_Window register Win7 Win6 From 0 to 255 msec with step of 1 msec. 36/ THSz3 Dur5 Dur4 Dur3 Lat5 Lat4 Lat3 Win5 Win4 Win3 LIS331DL THSz2 THSz1 THSz0 Dur2 Dur1 Dur0 Lat2 Lat1 Lat0 Win2 Win1 Win0 ...
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... LIS331DL 8 Typical performance characteristics 8.1 Mechanical characteristics at 25 °C Figure 12. X axis Zero-g level at 2 −150 −100 −50 0 Zero−g Level Offset [mg] Figure 14. Y axis Zero-g level at 2 −150 −100 −50 0 Zero−g Level Offset [mg] Figure 16. Z axis Zero-g level at 2.5 V ...
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... C] Figure 21. Y axis Sensitivity change Figure 23. Z axis Sensitivity change LIS331DL vs. temperature at 2.5 V −0.1 −0.05 0 0.05 0.1 o Sensitivity drift [%/ C] vs. temperature at 2.5 V −0.1 −0.05 0 0.05 0.1 o Sensitivity drift [%/ C] vs. temperature at 2.5 V −0.1 −0.05 0 0.05 0.1 o Sensitivity drift [%/ C] 0.15 0.15 0.15 ...
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... LIS331DL 8.3 Electrical characteristics at 25 °C Figure 24. Current consumption in normal mode at 2 200 220 240 260 280 300 Current consumption [uA] 320 340 360 380 400 Typical performance characteristics 39/42 ...
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... Typ. Max. 1.000 0.0394 0.785 0.0309 0.200 0.0079 1.000 1.060 0.0394 0.0417 2.000 2.060 0.0787 0.0811 0.500 0.0197 1.000 0.0394 0.875 0.0344 1.275 0.0502 0.150 0.0059 0.050 0.0020 LIS331DL Outline and mechanical data LGA16 (3x3x1.0mm) Land Grid Array Package 7983231 ® ...
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... LIS331DL 10 Revision history Table 58. Document revision history Date 28-Sep-2007 21-Jan-2008 16-Apr-2008 Revision 1 Initial release Updated package specification and package dimensions on page 2 Minor text changes to improve readability. Updated paragraph 2.1: Mechanical characteristics 3 section 8: Typical performance Updated POA Revision history Changes Figure 25: LGA 16: Mechanical data 40 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 42/42 Please Read Carefully: © 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com LIS331DL ...