MSC7118VF1200 Freescale Semiconductor, MSC7118VF1200 Datasheet

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... DMA and interrupt requests and trigger events such as interrupts, breakpoints, DMA transfers, or wake-up events; units operate independently, in sequence, or triggered externally; can be used standalone or with the OCE10. © Freescale Semiconductor, Inc., 2004, 2008. All rights reserved. Document Number: MSC7118 MSC7118 MAP-BGA–400 17 mm × ...

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... Figure 24. Test Access Port Timing Diagram . . . . . . . . . . . . . . . 38 Figure 25. TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 26. Voltage Sequencing Case Figure 27. Voltage Sequencing Case Figure 28. Voltage Sequencing Case Figure 29. Voltage Sequencing Case Figure 30. Voltage Sequencing Case Figure 31. PLL Power Supply Filter Circuits . . . . . . . . . . . . . . . . 46 Figure 32. SSTL Termination Techniques . . . . . . . . . . . . . . . . . . 52 Figure 33. SSTL Power Value . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Freescale Semiconductor ...

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... Instruction Cache (16 KB) Extended Core Interface M1 SRAM (256 KB) 128 Note: The arrows show the direction of the transfer. MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor DMA AMDMA ASM2 128 64 to IPBus 64 DSP ASEMI Core 64 IPBus ASTH AMIC 64 ...

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... DDC DDC COL TCK DDC DDC DDC DDC DDC T1TD TX_ER RXD2 RXD0 TX_EN CRS T1TFS TXD2 RXD3 TXD1 TXCLK RX_ER TXD3 RXCLK TXD0 RXD1 GND Freescale Semiconductor HA1 HREQ HDS HRW URXD V SSPLL DDPLL TEST0 HRESET TRST TDI MDC RX_DV ...

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... RXD2 W MDC RX_ER TXCLK TXD1 RXD3 Y RX_DV GND RXD1 TXD0 RXCLK Figure 3. MSC7118 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Bottom View GND HD0 HD1 HD4 HD6 HD7 ...

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... GND GPID8 GPOD8 DDM NC CS0 DQM2 DQS3 DQS0 CKE WE GPIC6 GPOC6 GPIC3 GPOC3 GPIC0 GPOC0 reserved reserved Hardware Controlled Primary Alternate HD15 HD12 HD10 HD7 HD6 HD4 HD1 HD0 reserved HD14 HD11 HD8 HD5 HD2 Freescale Semiconductor ...

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... C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled NC GPID7 GPOD7 D24 D30 D25 CS1 DQM3 DQM0 DQS1 ...

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... Interrupt GPO Enabled (Default) Enabled V DDM V DDIO V DDIO V DDIO V DDIO V DDIO V DDIO V DDC GND D26 D31 V DDM V DDM V DDC V DDC V DDC V DDC V DDM V DDIO V DDIO V DDIO V DDIO V DDIO V DDC V DDC DDM D15 D29 V DDC V DDC Hardware Controlled Primary Alternate Freescale Semiconductor ...

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... G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 H1 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled V DDC GND GND GND V DDM V DDM GND GND GND ...

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... DDM V DDM GND GND GND GND GND GND GND GND GND V DDIO V DDIO V DDC NC reserved reserved D10 V DDM D9 V DDM V DDM V DDM GND GND GND GND GND GND GND GND GND V DDIO V DDC Hardware Controlled Primary Alternate HA2 HA1 Freescale Semiconductor ...

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... K15 K16 K17 K18 K19 K20 L10 L11 L12 L13 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled GPIC11 GPOC11 reserved reserved D0 GND D8 V DDC V DDM GND GND ...

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... D5 V DDM V DDM GND GND GND GND GND GND GND GND GND GND V DDC V DDC IRQ15 GPOA14 IRQ3 GPOA12 IRQ2 GPOA13 REF V DDM V DDM V DDM GND GND GND Hardware Controlled Primary Alternate HCS2/HCS2 HCS1/HCS1 HRW or HRD/HRD SDA UTXD URXD Freescale Semiconductor ...

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... P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled GND GND GND GND GND V DDIO V DDC V DDC CLKIN ...

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... GND V DDM GND GND V DDIO GND V DDIO V DDIO V DDC TDO reserved TEST0 V DDM D20 D22 V DDM V DDM V DDC V DDM V DDM V DDC V DDM V DDM V DDIO V DDIO V DDIO V DDIO V DDC V DDC reserved TMS HRESET GND Hardware Controlled Primary Alternate EE0/DBREQ MDIO Freescale Semiconductor ...

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... V9 V10 V11 SWTE V12 GPIA8 V13 GPIA4 V14 GPIA0 V15 GPIA28 V16 V17 GPIA22 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled D21 D23 V DDM V DDC V DDC V DDC ...

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... NMI GPIC15 GPOC15 IRQ4 GPOA11 GPIA9 GPOA9 GPIA6 GPOA6 IRQ0 GPOA5 Hardware Controlled Primary Alternate TX_EN CRS EVNT1 CLKO EVNT2 T0RFS T0TFS T1RD T1TFS TXD2 reserved RXD3 reserved TXD1 TXCLK or REFCLK RX_ER MDC reserved EVNT3 T0RCK T0RD T0TD T1RCK Freescale Semiconductor ...

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... Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Signal Names Software Controlled ...

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... V 4.0 V 1.5 V –0.2 to 4.0 V (GND – 0.2) to 4.0 V 4.0 V 105 °C –40 °C –55 to +150 ° Value Unit 1.14 to 1.26 V DDC 2.38 to 2.63 V DDM 1.14 to 1.26 V 3.14 to 3.47 V DDIO 1.19 to 1.31 V REF T maximum: 105 ° minimum: –40 °C A Freescale Semiconductor ...

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... Input high CLKIN voltage DRAM interface input high I/O voltage DRAM interface input low I/O voltage Input leakage current DDIO V input leakage current REF MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor MAP-BGA 17 Symbol Natural Convection R θJA R θJA R θJB R θ ...

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... Peak-to-peak noise must not DDM DDM . REF Table 6. DDR DRAM Capacitance Typical Max Unit 0.09 1 µA 0.09 1 µA 0.09 1 µA 3.0 — 0.4 V 324.0 — the DRAM device at all times. ≤ OUT DDM Symbol Max Unit DIO Freescale Semiconductor ...

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... The rise and fall time of external clocks should maximum Characteristic CLKIN frequency CLKIN slope CLKIN frequency jitter (peak-to-peak) CLKO frequency jitter (peak-to-peak) MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor ) ns load ) ns load ) clocks. You must ensure that maximum frequency values are not exceeded (see CLKO Table 6 ...

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... MHz Input Division 100 MHz Input Division 100 MHz Input Division 100 MHz Input Division 100 MHz Input Division 100 MHz Input Division by 9 100 MHz Input Division The output F CLKIN when the RNG bit is set ( LOOP LOOP Comments Freescale Semiconductor /2 ...

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... DDR 266 (PC-2100) 83–133 MHz DDR 333 (PC-2600) 83–150 MHz MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Table 10. PLLMLTF Ranges Minimum PLLMLTF Value 266/Divided Input Clock . The minimum and maximum multiplication factors are dependent on the Loop Table 11 ...

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... External only Watchdog or Bus Yes Yes Yes Yes Yes Yes Yes must be asserted externally for at least 16 PORESET . V DD Soft Reset (HRESET) (SRESET) JTAG Command: EXTEST, CLAMP, or HIGHZ Monitor Yes No Yes Yes Yes Yes Yes Yes Yes Yes cycles after CLKIN Freescale Semiconductor ...

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... PORESET Input PORESET Internal HRESET Output (I/O) Figure 4. Timing Diagram for a Reset Configuration Write MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor C interface Characteristics Configuration Pins are sampled 2 Electrical Characteristics deassertion to define the boot and PORESET Expression ...

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... REF 0.3 REF DDM — 900 — 900 Min Max 10 — 6.67 — 0.5 × t – 1000 — CK 0.5 × t – 1000 — CK 0.5 × t – 1000 — CK 0.5 × t – 1000 — CK –600 600 Freescale Semiconductor Unit Unit ...

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... Figure 6 shows the DDR DRAM output timing diagram 204 206 An RAS CAS Write A0 WE CKE DQMn DQSn Dn Figure 6. DDR DRAM Output Timing Diagram MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Symbol 3 t DDKHDS, t DDKLDS 3 t DDKHDX, t DDKLDX t DDKHMP t DDKHME ...

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... DDR DRAM V ± 0.31 V REF 0.5 × V DDM Min Max 20.0 — 8.0 — 8.0 — 3.0 — 3.5 — 2.0 — 4.0 — — 14.0 2.0 — — 10.0 — 13.5 2.5 — 302 311 Freescale Semiconductor Unit V V Units ...

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... TDMxTCK TDMxTD TDMxRCK TDMxTFS (output) TDMxTFS (input) MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor 300 301 307 306 310 305 303 Figure 9. TDM Transmit Signals Electrical Characteristics 302 309 308 311 29 ...

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... 6.0 Note 11 CORE — 0.5 — 5.0 — 5.0 (3.0 × 6.0 Note 11 CORE (3.0 × 6.0 Note 11 CORE (2.0 × 1.0 Note 11 CORE (5.0 × 6.0 Note 11 CORE = 0 pF for minimum delay timings. L Freescale Semiconductor Unit ...

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... Figure 10. Read Timing Diagram, Single Data Strobe HA[0–2] HCS[1–2] HRD HD[0–15] HREQ (single host request) HRRQ (double host request) Figure 11. Read Timing Diagram, Double Data Strobe MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor HRW 44a HDS 51 ...

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... Figure 12. Write Timing Diagram, Single Data Strobe HA[0–2] HCS[1–2] HD[0–15] HREQ (single host request) HTRQ (double host request) Figure 13. Write Timing Diagram, Double Data Strobe MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev HWR Freescale Semiconductor ...

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... Figure 14. Host DMA Read Timing Diagram, HPCR[OAD HD[0–15] Figure 15. Host DMA Write Timing Diagram, HPCR[OAD MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor HREQ (Output) 64 44a RX[0–3] HACK Read 50 49 Data HD[0–15] Valid (Output) ...

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... C K Data Byte Data Byte 2 Figure 16 Timing Diagram Fast Max 400 — — — — BCK — — 700 300 — — Stop Condition Start Condition 457 459 460 Freescale Semiconductor Unit kHz μs μs μs μs μ μs μs ...

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... Configure the direction of the EE pin in the EE_CTRL register (see the SC140/SC1400 Core Reference Manual for details. 3. Refer to Table 1-11 on page 1-16 for details on EE pin functionality. Figure 20 shows the signal behavior of the EE0 In EE0 Out MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Table 23. UART Timing Expression F /2 CORE T APBCLK 16 × ...

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... Table 26. GPIO Signal Timing Type Asynchronous Synchronous to core clock Asynchronous Asynchronous pins. GPI/GPO 601 602 Figure 21. GPI/GPO Pin Timing Min 1.5 × APBCLK periods 1 APBCLK period Min 1.5 × APBCLK periods 1 APBCLK period 1.5 × APBCLK periods 3 × APBCLK periods 6 Freescale Semiconductor ...

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... All timings apply to OCE module data transfers as the OCE module uses the JTAG port as an interface. TCK (Input) Figure 22. Test Clock Input Timing Diagram MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Table 27. JTAG Timing × 1.6 V ...

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... TRST (Input) 712 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev 704 Input Data Valid 706 Output Data Valid 707 708 Input Data Valid 710 Output Data Valid 711 Figure 25. TRST Timing Diagram V IH 705 V IH 709 Freescale Semiconductor ...

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... Use the following equation to determine T where T = thermocouple (or infrared) temperature on top of the package (°C) T Ψ = thermal characterization parameter (°C/ power dissipation in the package (W) D MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor in °C can be obtained from the following × P θ ...

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... Table 28. MSC7118 Voltages Symbol V DDC V DDM V REF V DDIO and GND. The memory and reference voltages supply DDIO DDM and 0.51 × Refer to the JEDEC standard JESD8 DDM DDM Value 1.2 V 2.5 V 1.25 V 3.3 V DDC and GND . The reference voltage Freescale Semiconductor ...

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... Refer to Figure 26 for relative timing for power sequencing case 1. Ramp-up <10 ms <10 ms MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor and V DDIO <10 ms Time Figure 26. Voltage Sequencing Case 1 Hardware Design Considerations is less than 10 ms. ...

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... V) supplies simultaneously (second). DDM and V DDIO and V DDIO <10 ms Time Figure 27. Voltage Sequencing Case less than 10 ms. DDC DDM is less than 10 ms. DDC and V is less than 10 ms for DDC DDM Ramp-down V = 3.3 V DDIO V = 2.5 V DDM V = 1.25 V REF V = 1.2 V DDC <10 ms Freescale Semiconductor ...

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... Make sure that the time interval between the ramp-up or ramp-down time for V power-up and power-down. • Refer to Figure 28 for relative timing for Case 3. Ramp-up <10 ms <10 ms MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor (1.25 V) supplies simultaneously (third). REF and V DDIO (1.25 V) supplies simultaneously (first). REF and V DDIO < ...

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... REF and V DDIO (1.25 V), and V (2.5 V) supplies simultaneously (first). REF DDM Time Figure 29. Voltage Sequencing Case 4 is less than 10 ms. DDC and V is less than 10 ms for DDC DDM Ramp-down V = 3.3 V DDIO V = 2.5 V DDM V = 1.25 V REF V = 1.2 V DDC <10 ms Freescale Semiconductor ...

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... If a design uses case 5, it must accommodate DDM the potential current spikes. Verify risks related to current spikes using actual information for the specific application. MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor and V DDIO and V DDIO < ...

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... GND GND can be tied directly to the SSPLL Ω 2 0.1 µF 0.01 µF 10 µF GND planes is recommended. See Section 3.5 V DDPLL plane. A circuit similar to the one GND pin (which are V DDPLL V . These traces DDC V DDPLL CLKO pin. Freescale Semiconductor pin ...

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... V, and the core frequency is 300 MHz. This yields: = 750 pF × (1 CORE This equation allows for adjustments to voltage and frequency if necessary. MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Symbol Nominal Voltage V 1.2 V DDC V 2 ...

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... DDRIO STATIC DYNAMIC = (unused pins × % driven high) × × 2 × 300 MHz × × 25 MHz × 10 –3 = 5.44 mW per I/O line 2 C module. Eqn. 6 Eqn. 7 Eqn. 8 –3 mW Eqn. 9 Eqn × 300 × 10 – 326.3 mW Eqn. 11 Eqn. 12 Freescale Semiconductor ...

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... Configures HDI16 strobe polarity. H8BIT Configures HDI16 operation mode. MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor , take care when driving many buffers that implement input bus-hold circuitry. The Table 30. Reset Configuration Signals See Table 31 for details. ...

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... C is limited to a maximum bit rate of 400 Kbps. With a clock divider of 128, this limits the maximum input clock frequency to 100 MHz. — — — — — — — — — — pin. Thus, the device operates CLKIN 2 C port. The PORESET, as shown in Table 31. Freescale Semiconductor ...

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... Alternate set: UTXD, URXD, SDA, and SCL, which cannot be used with the PLL. In either configuration, an error during SPI boot is flagged on the EVNT3 pin. For details on the boot procedure, see the “Boot Program” chapter of the MSC711x Reference Manual. MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor pin. H8BIT and pins ...

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... Typical values for the resistors are as follows Ω • Ω • MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev DDR RS Bank SSTL_2 SSTL_2 RS SSTL_2 DDR RS Bank SSTL_2 SSTL_2 RS SSTL_2 Figure 32. SSTL Termination Techniques V TT Generator DDR RT Bank Generator DDR RT Bank RT Freescale Semiconductor ...

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... TT termination rail. • See the Micron DesignLine publication entitled Decoupling Capacitor Calculation for a DDR Memory Channel ( http://download.micron.com/pdf/pubs/designline/3Q00dl1-4.pdf ). MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Figure 33 ...

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... Route address and control on separate critical layers. — If resistor networks (RNs) are used, attempt to keep data and command lines in separate packages. MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev DQS + the same layer. Avoid switching layers within a byte group. Freescale Semiconductor ...

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... Array (MAP-BGA) Ordering Information , so it should be PORESET is deasserted. After PORESET is deasserted, so they should be tied to PORESET HTRQ/HTRQ signals require a pull-up resistor. pins should be pulled up or down, H8BIT to one of the EVNT DONE Core Solder Spheres Order Number (MHz) 300 Lead-free MSC7118VM1200 Lead-bearing MSC7118VF1200 55 ...

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... All dimensions in millimeters. 2. Dimensioning and tolerancing per ASME Y14.5M–1994. 3. Maximum solder ball diameter measured parallel to Datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package. Freescale Semiconductor ...

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... Change the PLL filter resistor from 20 Ω Ω in Section 3.2.5. 7 Apr 2008 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Table 32. Document Revision History Description and V in the new power supply design recommendation Section CCSYN ...

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... Revision History MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Freescale Semiconductor ...

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... MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Revision History 59 ...

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... For information on Freescale’s Environmental Products program http://www.freescale.com/epp. Freescale™, the Freescale logo, CodeWarrior, fieldBIST, and StarCore are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004, 2008. All rights reserved. ...