KMSC7119VM1200 Freescale Semiconductor, KMSC7119VM1200 Datasheet

DSP 16BIT W/DDR CTRLR 400-MAPBGA

KMSC7119VM1200

Manufacturer Part Number
KMSC7119VM1200
Description
DSP 16BIT W/DDR CTRLR 400-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MSC711x StarCorer
Type
Fixed Pointr
Datasheet

Specifications of KMSC7119VM1200

Interface
Host Interface, I²C, UART
Clock Rate
300MHz
Non-volatile Memory
ROM (8 kB)
On-chip Ram
464kB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Operating Temperature
-40°C ~ 105°C
Mounting Type
*
Package / Case
400-MAPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
KMSC7119VM1200
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor
Data Sheet
Low-Cost 16-bit DSP with
DDR Controller and 10/100
Mbps Ethernet MAC
• StarCore
• 192 Kbyte M2 memory for critical data and temporary data
• 8 Kbyte boot ROM.
• AHB-Lite crossbar switch that allows parallel data transfers
• Internal PLL generates up to 300 MHz clock for the SC1400 core
• Clock synthesis module provides predivision of PLL input clock;
• Enhanced 16-bit wide host interface (HDI16) provides a glueless
• DDR memory controller that supports byte enables for up to a
• Programmable memory interface with independent read buffers,
• System control unit performs software watchdog timer function;
• Event port collects and counts important signal events including
© Freescale Semiconductor, Inc., 2004, 2008. All rights reserved.
core, 256 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte
instruction cache (ICache), four-entry write buffer, programmable
interrupt controller (PIC), and low-power Wait and Stop
processing modes.
buffering.
between four master ports and six slave ports, where each port
connects to an AHB-Lite bus; fixed or round robin priority
programmable at each slave port; programmable bus parking at
each slave port; low power mode.
and up to 150 MHz for the crossbar switch, DMA channels, M2
memory, and other peripherals.
independent clocking of the internal timers and DDR module;
programmable operation in the SC1400 low power Stop mode;
independent shutdown of different regions of the device.
connection to industry-standard microcomputers,
microprocessors, and DSPs and can also operate with an 8-bit host
data bus, making if fully compatible with the DSP56300 HI08
from the external host side.
32-bit data bus; glueless interface to 150 MHz 14-bit page mode
DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte;
and 16-bit or 32-bit external data bus.
programmable predictive read feature for each buffer, and a write
buffer.
includes programmable bus time-out monitors on AHB-Lite slave
buses; includes bus error detection and programmable time-out
monitors on AHB-Lite master buses; and has address
out-of-range detection on each crossbar switch buses.
DMA and interrupt requests and trigger events such as interrupts,
breakpoints, DMA transfers, or wake-up events; units operate
independently, in sequence, or triggered externally; can be used
standalone or with the OCE10.
®
SC1400 DSP extended core with one SC1400 DSP
• Multi-channel DMA controller with 32 time-multiplexed
• Two independent TDM modules with independent receive and
• Ethernet controller with support for 10/100 Mbps MII/RMII
• UART with full-duplex operation up to 5.0 Mbps.
• Up to 41 general-purpose input/output (GPIO) ports.
• I
• Two quad timer modules, each with sixteen configurable 16-bit
• fieldBIST™ unit detects and provides visibility into unlikely field
• Standard JTAG interface allows easy integration to system
• Optional booting external host via 8-bit or 16-bit access through
unidirectional channels, priority-based time-multiplexing
between channels using 32 internal priority levels, fixed- or
round-robin-priority operation, major-minor loop structure, and
DONE or DRACK protocol from requesting units.
transmit, programmable sharing of frame sync and clock,
programmable word size (8 or 16-bit), hardware-base
A-law/μ-law conversion, up to 50 Mbps data rate per TDM, up to
128 channels, with glueless interface to E1/T1 frames and MVIP,
SCAS, and H.110 buses.
designed to comply with IEEE Std. 802.3™, 802.3u™, 802.3x™,
and 802.3ac™; with internal receive and transmit FIFOs and a
FIFO controller; direct access to internal memories via its own
DMA controller; full and half duplex operation; programmable
maximum frame length; virtual local area network (VLAN) tag
and priority support; retransmission of transmit FIFO following
collision; CRC generation and verification for inbound and
outbound packets; and address recognition including
promiscuous, broadcast, individual address. hash/exact match,
and multicast hash match.
Mbyte.
timers.
failures for systems with high availability to ensure structural
integrity, that the device operates at the rated speed, is free from
reliability defects, and reports diagnostics for partial or complete
device inoperability.
firmware and internal on-chip emulation (OCE10) module.
the HDI16, I
Flash/EEPROM devices; different clocking options during boot
with the PLL on or off using a variety of input frequency ranges.
2
C interface that allows booting from EEPROM devices up to 1
2
C, or SPI using in the boot ROM to access serial SPI
MSC7119
Document Number: MSC7119
MAP-BGA–400
17 mm × 17 mm
Rev. 8, 4/2008

Related parts for KMSC7119VM1200

KMSC7119VM1200 Summary of contents

Page 1

... DMA and interrupt requests and trigger events such as interrupts, breakpoints, DMA transfers, or wake-up events; units operate independently, in sequence, or triggered externally; can be used standalone or with the OCE10. © Freescale Semiconductor, Inc., 2004, 2008. All rights reserved. Document Number: MSC7119 MSC7119 MAP-BGA–400 17 mm × ...

Page 2

... Figure 29. TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 30. Voltage Sequencing Case Figure 31. Voltage Sequencing Case Figure 32. Voltage Sequencing Case Figure 33. Voltage Sequencing Case Figure 34. Voltage Sequencing Case Figure 35. PLL Power Supply Filter Circuits . . . . . . . . . . . . . . . . 48 Figure 36. SSTL Termination Techniques . . . . . . . . . . . . . . . . . . 54 Figure 37. SSTL Power Value . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor ...

Page 3

... Core Trace Buffer (8 KB) Fetch Unit Instruction Cache (16 KB) Extended Core Interface M1 SRAM (256 KB) 128 Note: The arrows show the direction of the transfer. Freescale Semiconductor DMA AMDMA ASM2 128 64 to IPBus 64 DSP ASEMI Core 64 IPBus ASTH AMIC 64 128 AMEC ASAPB 64 32 ...

Page 4

... DDC DDC COL TCK DDC DDC DDC DDC DDC T1TD TX_ER RXD2 RXD0 TX_EN CRS T1TFS TXD2 RXD3 TXD1 TXCLK RX_ER TXD3 RXCLK TXD0 RXD1 GND Freescale Semiconductor HA1 HREQ HDS HRW URXD V SSPLL DDPLL TEST0 HRESET TRST TDI MDC RX_DV ...

Page 5

... DD V TDI CRS TX_EN RXD0 RXD2 W MDC RX_ER TXCLK TXD1 RXD3 Y RX_DV GND RXD1 TXD0 RXCLK Figure 3. MSC7119 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View Freescale Semiconductor Bottom View GND HD0 HD1 HD4 HD6 HD7 HD10 BM2 NC HD2 HD5 HD8 ...

Page 6

... GND GPID8 GPOD8 DDM NC CS0 DQM2 DQS3 DQS0 CKE WE GPIC6 GPOC6 GPIC3 GPOC3 GPIC0 GPOC0 reserved reserved MSC7119 Data Sheet, Rev. 8 Hardware Controlled Primary Alternate HD15 HD12 HD10 HD7 HD6 HD4 HD1 HD0 reserved HD14 HD11 HD8 HD5 HD2 Freescale Semiconductor ...

Page 7

... B19 B20 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled NC GPID7 GPOD7 D24 D30 D25 CS1 DQM3 DQM0 DQS1 RAS CAS GPIC5 GPOC5 GPIC1 GPOC1 reserved NC NC ...

Page 8

... Enabled V DDM V DDIO V DDIO V DDIO V DDIO V DDIO V DDIO V DDC GND D26 D31 V DDM V DDM V DDC V DDC V DDC V DDC V DDM V DDIO V DDIO V DDIO V DDIO V DDIO V DDC V DDC DDM D15 D29 V DDC V DDC MSC7119 Data Sheet, Rev. 8 Hardware Controlled Primary Alternate Freescale Semiconductor ...

Page 9

... F15 F16 F17 F18 F19 F20 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 H1 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled V DDC GND GND GND V DDM V DDM GND GND GND V DDIO V DDC V DDC NC NC ...

Page 10

... GND GND GND GND GND GND GND V DDIO V DDIO V DDC NC reserved reserved D10 V DDM D9 V DDM V DDM V DDM GND GND GND GND GND GND GND GND GND V DDIO V DDC MSC7119 Data Sheet, Rev. 8 Hardware Controlled Primary Alternate HA2 HA1 Freescale Semiconductor ...

Page 11

... K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 L10 L11 L12 L13 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled GPIC11 GPOC11 reserved reserved D0 GND D8 V DDC V DDM GND GND GND GND GND GND GND ...

Page 12

... GND GND GND GND GND GND GND GND GND V DDC V DDC IRQ15 GPOA14 IRQ3 GPOA12 IRQ2 GPOA13 REF V DDM V DDM V DDM GND GND GND MSC7119 Data Sheet, Rev. 8 Hardware Controlled Primary Alternate HCS2/HCS2 HCS1/HCS1 HRW or HRD/HRD SDA UTXD URXD Freescale Semiconductor ...

Page 13

... N18 N19 GPIA15 N20 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled GND GND GND GND GND V DDIO V DDC V DDC CLKIN IRQ14 GPOA15 V SSPLL D7 D17 D16 V DDM V ...

Page 14

... DDIO GND V DDIO V DDIO V DDC TDO reserved TEST0 V DDM D20 D22 V DDM V DDM V DDC V DDM V DDM V DDC V DDM V DDM V DDIO V DDIO V DDIO V DDIO V DDC V DDC reserved TMS HRESET GND MSC7119 Data Sheet, Rev. 8 Hardware Controlled Primary Alternate EE0/DBREQ MDIO Freescale Semiconductor ...

Page 15

... U16 U17 U18 U19 U20 V10 V11 SWTE V12 GPIA8 V13 GPIA4 V14 GPIA0 V15 GPIA28 V16 V17 GPIA22 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled D21 D23 V DDM V DDC V DDC V DDC V DDC V DDC V DDC V DDC V DDC V ...

Page 16

... GPOA11 GPIA9 GPOA9 GPIA6 GPOA6 IRQ0 GPOA5 MSC7119 Data Sheet, Rev. 8 Hardware Controlled Primary Alternate TX_EN CRS EVNT1 CLKO EVNT2 T0RFS T0TFS T1RD T1TFS TXD2 reserved RXD3 reserved TXD1 TXCLK or REFCLK RX_ER MDC reserved EVNT3 T0RCK T0RD T0TD T1RCK Freescale Semiconductor ...

Page 17

... The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. Freescale Semiconductor Signal Names Software Controlled ...

Page 18

... V 4.0 V 1.5 V –0.2 to 4.0 V (GND – 0.2) to 4.0 V 4.0 V 105 °C –40 °C –55 to +150 ° Value Unit 1.14 to 1.26 V DDC 2.38 to 2.63 V DDM 1.14 to 1.26 V 3.14 to 3.47 V DDIO 1.19 to 1.31 V REF T maximum: 105 ° minimum: –40 °C A Freescale Semiconductor ...

Page 19

... DRAM interface I/O reference voltage 3 DRAM interface I/O termination voltage Input high CLKIN voltage DRAM interface input high I/O voltage DRAM interface input low I/O voltage Input leakage current DDIO V input leakage current REF Freescale Semiconductor MAP-BGA 17 Symbol Natural Convection R θJA R θJA R θJB R θJC Ψ ...

Page 20

... Peak-to-peak noise must not DDM DDM . REF Table 6. DDR DRAM Capacitance MSC7119 Data Sheet, Rev. 8 Typical Max Unit 0.09 1 µA 0.09 1 µA 0.09 1 µA 3.0 — 0.4 V 324.0 — the DRAM device at all times. ≤ OUT DDM Symbol Max Unit DIO Freescale Semiconductor ...

Page 21

... Note: The rise and fall time of external clocks should maximum Characteristic CLKIN frequency CLKIN slope CLKIN frequency jitter (peak-to-peak) CLKO frequency jitter (peak-to-peak) Freescale Semiconductor ) ns load ) ns load ) clocks. You must ensure that maximum frequency values are not exceeded (see CLKO Table 6. Maximum Frequencies Table 7 ...

Page 22

... Input Division 100 MHz Input Division 100 MHz Input Division 100 MHz Input Division 100 MHz Input Division by 9 100 MHz Input Division by 10 MSC7119 Data Sheet, Rev The output F CLKIN when the RNG bit is set ( LOOP LOOP Comments Freescale Semiconductor /2 ...

Page 23

... Range for DDR CK DDR 200 (PC-1600) 83–100 MHz DDR 266 (PC-2100) 83–133 MHz DDR 333 (PC-2600) 83–150 MHz Freescale Semiconductor Table 10. PLLMLTF Ranges Minimum PLLMLTF Value 266/Divided Input Clock . The minimum and maximum multiplication factors are dependent on the Loop Table 11. F Frequency Ranges ...

Page 24

... Yes Yes Yes must be asserted externally for at least 16 PORESET . V DD MSC7119 Data Sheet, Rev. 8 Hard Reset Soft Reset (HRESET) (SRESET) External or JTAG Command: EXTEST, CLAMP, or HIGHZ Monitor Yes No Yes Yes Yes Yes Yes Yes Yes Yes cycles after CLKIN Freescale Semiconductor ...

Page 25

... Timings are not tested, but are guaranteed by design. 1 PORESET Input PORESET Internal HRESET Output (I/O) Figure 4. Timing Diagram for a Reset Configuration Write Freescale Semiconductor C interface Characteristics Configuration Pins are sampled 2 MSC7119 Data Sheet, Rev. 8 Electrical Characteristics deassertion to define the boot and ...

Page 26

... REF 0.3 REF DDM — 900 — 900 Min Max 10 — 6.67 — 0.5 × t – 1000 — CK 0.5 × t – 1000 — CK 0.5 × t – 1000 — CK 0.5 × t – 1000 — CK –600 600 Freescale Semiconductor Unit Unit ...

Page 27

... This is already guaranteed by the memory controller operation. Figure 6 shows the DDR DRAM output timing diagram 204 206 An RAS CAS Write A0 WE CKE DQMn DQSn Dn Figure 6. DDR DRAM Output Timing Diagram Freescale Semiconductor Symbol 3 t DDKHDS, t DDKLDS 3 t DDKHDX, t DDKLDX t DDKHMP t DDKHME ...

Page 28

... DDR DRAM V ± 0.31 V REF 0.5 × V DDM Min Max 20.0 — 8.0 — 8.0 — 3.0 — 3.5 — 2.0 — 4.0 — — 14.0 2.0 — — 10.0 — 13.5 2.5 — 302 311 Freescale Semiconductor Unit V V Units ...

Page 29

... RXDn, RX_DV, CRS_DV, RX_ER to receive clock rising edge setup time 804 Receive clock rising edge to RXDn, RX_DV, CRS_DV, RX_ER hold time Receive clock RXDn RX_DV CRS_DV RX_ER Freescale Semiconductor 300 301 307 306 310 305 303 Figure 9. TDM Transmit Signals Table 21. Receive Signal Timing ...

Page 30

... Figure 12. Asynchronous Input Signal Timing 30 Table 22. Transmit Signal Timing Characteristics 800 801 806 805 Figure 11. Ethernet Receive Signal Timing Characteristics MSC7119 Data Sheet, Rev. 8 Min Max Unit 40 — 20 — — 7 — — 7 — 4 — — 14 802 Valid Min Max Unit 60 — 30 — 807 Freescale Semiconductor ...

Page 31

... MDIO input to MDC rising edge setup time 814 MDC rising edge to MDIO input hold time MDC (output) MDIO (output) MDIO (input) Figure 13. Serial Management Channel Timing Freescale Semiconductor Characteristics 808 809 811 813 814 MSC7119 Data Sheet, Rev. 8 Electrical Characteristics ...

Page 32

... 6.0 Note 11 CORE — 0.5 — 5.0 — 5.0 (3.0 × 6.0 Note 11 CORE (3.0 × 6.0 Note 11 CORE (2.0 × 1.0 Note 11 CORE (5.0 × 6.0 Note 11 CORE = 0 pF for minimum delay timings. L Freescale Semiconductor Unit ...

Page 33

... HREQ (single host request) HRRQ (double host request) Figure 14. Read Timing Diagram, Single Data Strobe HA[0–2] HCS[1–2] HRD HD[0–15] HREQ (single host request) HRRQ (double host request) Figure 15. Read Timing Diagram, Double Data Strobe Freescale Semiconductor HRW 44a HDS 51 55 ...

Page 34

... HREQ (single host request) HTRQ (double host request) Figure 16. Write Timing Diagram, Single Data Strobe HA[0–2] HCS[1–2] HD[0–15] HREQ (single host request) HTRQ (double host request) Figure 17. Write Timing Diagram, Double Data Strobe HWR 47 MSC7119 Data Sheet, Rev Freescale Semiconductor ...

Page 35

... Figure 18. Host DMA Read Timing Diagram, HPCR[OAD HD[0–15] Figure 19. Host DMA Write Timing Diagram, HPCR[OAD Freescale Semiconductor HREQ (Output) 64 44a RX[0–3] HACK Read 50 49 Data HD[0–15] Valid (Output) HREQ (Output TX[0–3] Write HACK 47 Data Valid (Input) MSC7119 Data Sheet, Rev. 8 ...

Page 36

... Data Byte 2 Figure 20 Timing Diagram MSC7119 Data Sheet, Rev. 8 Fast Max 400 — — — — BCK — — 700 300 — — Stop Condition Start Condition 457 459 460 Freescale Semiconductor Unit kHz μs μs μs μs μ μs μs ...

Page 37

... Configure the direction of the EE pin in the EE_CTRL register (see the SC140/SC1400 Core Reference Manual for details. 3. Refer to Table 1-11 on page 1-16 for details on EE pin functionality. Figure 24 shows the signal behavior of the EE0 In EE0 Out Freescale Semiconductor Table 27. UART Timing Expression F /2 CORE ...

Page 38

... Asynchronous Synchronous to core clock Asynchronous Asynchronous pins. GPI/GPO 601 602 Figure 25. GPI/GPO Pin Timing MSC7119 Data Sheet, Rev. 8 Min 1.5 × APBCLK periods 1 APBCLK period Min 1.5 × APBCLK periods 1 APBCLK period 1.5 × APBCLK periods 3 × APBCLK periods 6 Freescale Semiconductor ...

Page 39

... TCK low to TDO high impedance 712 TRST assert time Note: All timings apply to OCE module data transfers as the OCE module uses the JTAG port as an interface. TCK (Input) Figure 26. Test Clock Input Timing Diagram Freescale Semiconductor Table 31. JTAG Timing × 1 701 V ...

Page 40

... Figure 28. Test Access Port Timing Diagram TRST (Input) 712 40 704 Input Data Valid 706 Output Data Valid 707 708 Input Data Valid 710 Output Data Valid 711 Figure 29. TRST Timing Diagram MSC7119 Data Sheet, Rev 705 V IH 709 Freescale Semiconductor ...

Page 41

... Use the following equation to determine T where T = thermocouple (or infrared) temperature on top of the package (°C) T Ψ = thermal characterization parameter (°C/ power dissipation in the package (W) D Freescale Semiconductor in °C can be obtained from the following × P θ ...

Page 42

... DDC V DDM V REF V DDIO and GND. The memory and reference voltages supply DDIO and 0.51 × V DDM DDM MSC7119 Data Sheet, Rev. 8 Value 1.2 V 2.5 V 1.25 V 3.3 V DDC and GND . The reference voltage DDM . Refer to the JEDEC standard JESD8 Freescale Semiconductor ...

Page 43

... Make sure that the time interval between the ramp-up or ramp-down for V power-up and power-down. • Refer to Figure 30 for relative timing for power sequencing case 1. Ramp-up <10 ms <10 ms Freescale Semiconductor and V DDIO <10 ms Time Figure 30. Voltage Sequencing Case 1 MSC7119 Data Sheet, Rev. 8 Hardware Design Considerations is less than 10 ms ...

Page 44

... V DDIO <10 ms Time Figure 31. Voltage Sequencing Case 2 MSC7119 Data Sheet, Rev less than 10 ms. DDC DDM is less than 10 ms. DDC and V is less than 10 ms for DDC DDM Ramp-down V = 3.3 V DDIO V = 2.5 V DDM V = 1.25 V REF V = 1.2 V DDC <10 ms Freescale Semiconductor ...

Page 45

... Make sure that the time interval between the ramp-up or ramp-down time for V power-up and power-down. • Refer to Figure 32 for relative timing for Case 3. Ramp-up <10 ms <10 ms Freescale Semiconductor (1.25 V) supplies simultaneously (third). REF and V DDIO (1.25 V) supplies simultaneously (first). REF and V DDIO < ...

Page 46

... V), and V (2.5 V) supplies simultaneously (first). REF DDM Time Figure 33. Voltage Sequencing Case 4 MSC7119 Data Sheet, Rev less than 10 ms. DDC and V is less than 10 ms for DDC DDM Ramp-down V = 3.3 V DDIO V = 2.5 V DDM V = 1.25 V REF V = 1.2 V DDC <10 ms Freescale Semiconductor ...

Page 47

... Cases and 4 are recommended for system design. Designs that use Case 5 may have large current spikes on the V supply at startup and is not recommended for most designs design uses case 5, it must accommodate DDM the potential current spikes. Verify risks related to current spikes using actual information for the specific application. Freescale Semiconductor and V DDIO and V DDIO < ...

Page 48

... SSPLL Ω 2 0.1 µF 0.01 µF 10 µF MSC7119 Data Sheet, Rev. 8 GND planes is recommended. See Section 3.5 V DDPLL plane. A circuit similar to the one GND pin (which are V DDPLL V . These traces DDC V DDPLL CLKO pin. Freescale Semiconductor pin ...

Page 49

... Estimation of core power is straightforward. It uses the generic dynamic power equation and assumes that the core load capacitance is 750 pF, core voltage swing is 1.2 V, and the core frequency is 300 MHz. This yields: = 750 pF × (1 CORE This equation allows for adjustments to voltage and frequency if necessary. Freescale Semiconductor Symbol Nominal Voltage V 1.2 V DDC V 2 ...

Page 50

... DDRIO STATIC DYNAMIC = (unused pins × % driven high) × × 2 × 300 MHz × × 25 MHz × 10 –3 = 5.44 mW per I/O line MSC7119 Data Sheet, Rev. 8 Eqn. 6 Eqn. 7 Eqn. 8 –3 mW Eqn. 9 Eqn × 300 × 10 – 326.3 mW Eqn. 11 Eqn. 12 Freescale Semiconductor ...

Page 51

... Determines boot mode. SWTE Determines watchdog functionality. HDSP Configures HDI16 strobe polarity. H8BIT Configures HDI16 operation mode. Freescale Semiconductor , take care when driving many buffers that implement input bus-hold circuitry. The Table 34. Reset Configuration Signals See Table 35 for details. 0 Watchdog timer disabled. 1 Watchdog timer enabled ...

Page 52

... C is limited to a maximum bit rate of 400 Kbps. With a clock divider of 128, this limits the maximum input clock frequency to 100 MHz. — — — — — — — — — — pin. Thus, the device operates CLKIN 2 C port. The PORESET, as shown in Table 35. Freescale Semiconductor ...

Page 53

... Alternate set: UTXD, URXD, SDA, and SCL, which cannot be used with the PLL. In either configuration, an error during SPI boot is flagged on the EVNT3 pin. For details on the boot procedure, see the “Boot Program” chapter of the MSC711x Reference Manual. Freescale Semiconductor pin. H8BIT and pins ...

Page 54

... Typical values for the resistors are as follows Ω • Ω • DDR RS Bank SSTL_2 SSTL_2 RS SSTL_2 DDR RS Bank SSTL_2 SSTL_2 RS SSTL_2 Figure 36. SSTL Termination Techniques MSC7119 Data Sheet, Rev Generator DDR RT Bank Generator DDR RT Bank RT Freescale Semiconductor ...

Page 55

... Leverage V island topology to minimize the number of capacitors required to supply the burst current needs of the TT termination rail. • See the Micron DesignLine publication entitled Decoupling Capacitor Calculation for a DDR Memory Channel (http://download.micron.com/pdf/pubs/designline/3Q00dl1-4.pdf). Freescale Semiconductor Figure 37. SSTL Power Value as a high current power source. This section outlines TT DC offsets ...

Page 56

... If stack-up allows, keep DDR data groups away from the address and control nets. — Route address and control on separate critical layers. — If resistor networks (RNs) are used, attempt to keep data and command lines in separate packages. 56 DQS + the same layer. Avoid switching layers within a byte group. MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor ...

Page 57

... Do not connect DBREQ pins, and to DBREQ HRRQ 4 Ordering Information Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order. Part Supply Voltage MSC7119 1.2 V core Molded Array Process-Ball Grid 2.5 V memory 3.3 V I/O Freescale Semiconductor pins must be pulled up ...

Page 58

... All dimensions in millimeters. 2. Dimensioning and tolerancing per ASME Y14.5M–1994. 3. Maximum solder ball diameter measured parallel to Datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package. Freescale Semiconductor ...

Page 59

... Section 3.2 has been clarified by adding subsection headings. • Change the PLL filter resistor from 20 Ω Ω in Section 3.2.5. 8 Apr 2008 Freescale Semiconductor Table 36. Document Revision History Description and V in the new power supply design recommendation Section CCSYN CCSYN1 MSC7119 Data Sheet, Rev ...

Page 60

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

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