Manufacturer Part NumberXC6VLX130T-L1FFG484I
DescriptionIC FPGA VIRTEX 6 128K 484FFGBGA
ManufacturerXilinx Inc
SeriesVirtex™ 6 LXT
XC6VLX130T-L1FFG484I datasheet

Specifications of XC6VLX130T-L1FFG484I

Number Of Logic Elements/cells128000Number Of Labs/clbs10000
Total Ram Bits9732096Number Of I /o240
Voltage - Supply0.91 V ~ 0.97 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case484-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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DS150 (v2.2) January 28, 2010
General Description
The Virtex®-6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon
foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on
innovation as soon as their development cycle begins. Using the third-generation ASMBL™ (Advanced Silicon Modular Block) column-
based architecture, the Virtex-6 family contains multiple distinct sub-families. This overview covers the devices in the LXT, SXT, and HXT
sub-families. Each sub-family contains a different ratio of features to most efficiently address the needs of a wide variety of advanced logic
designs. In addition to the high-performance logic fabric, Virtex-6 FPGAs contain many built-in system-level blocks. These features allow
logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 40 nm state-of-the-
art copper process technology, Virtex-6 FPGAs are a programmable alternative to custom ASIC technology. Virtex-6 FPGAs offer the best
solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance
embedded systems designers with unprecedented logic, DSP, connectivity, and soft microprocessor capabilities.
Summary of Virtex-6 FPGA Features
Three sub-families:
Virtex-6 LXT FPGAs: High-performance logic with
advanced serial connectivity
Virtex-6 SXT FPGAs: Highest signal processing
capability with advanced serial connectivity
Virtex-6 HXT FPGAs: Highest bandwidth serial
Compatibility across sub-families
LXT and SXT devices are footprint compatible in
the same package
Advanced, high-performance FPGA Logic
Real 6-input look-up table (LUT) technology
Dual LUT5 (5-input LUT) option
LUT/dual flip-flop pair for applications requiring rich
register mix
Improved routing efficiency
64-bit (or two 32-bit) distributed LUT RAM option
per 6-input LUT
SRL32/dual SRL16 with registered outputs option
Powerful mixed-mode clock managers (MMCM)
MMCM blocks provide zero-delay buffering,
frequency synthesis, clock-phase shifting, input-
jitter filtering, and phase-matched clock division
36-Kb block RAM/FIFOs
Dual-port RAM blocks
Dual-port widths up to 36 bits
Simple dual-port widths up to 72 bits
Enhanced programmable FIFO logic
Built-in optional error-correction circuitry
Optionally use each block as two independent
18 Kb blocks
High-performance parallel SelectIO
1.2 to 2.5V I/O operation
Source-synchronous interfacing using
ChipSync™ technology
Digitally controlled impedance (DCI) active
Flexible fine-grained I/O banking
High-speed memory interface support with
integrated write-leveling capability
© 2009–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. PCI, PCIe and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS150 (v2.2) January 28, 2010
Advance Product Specification
Advanced DSP48E1 slices
Flexible configuration options
System Monitor capability on all devices
Integrated interface blocks for PCI Express
GTX transceivers: up to 6.6 Gb/s
GTH transceivers: 2.488 Gb/s to beyond 11 Gb/s
Integrated 10/100/1000 Mb/s Ethernet MAC block
40 nm copper CMOS process technology
1.0V core voltage (-1, -2, -3 speed grades only)
Lower-power 0.9V core voltage option (-1L speed
grade only)
High signal-integrity flip-chip packaging available in
standard or Pb-free package options
Virtex-6 Family Overview
Advance Product Specification
25 x 18, two's complement multiplier/accumulator
Optional pipelining
New optional pre-adder to assist filtering
Optional bitwise logic functionality
Dedicated cascade connections
SPI and Parallel Flash interface
Multi-bitstream support with dedicated fallback
reconfiguration logic
Automatic bus width detection
On-chip/off-chip thermal and supply voltage
JTAG access to all monitored quantities
Compliant to the PCI Express Base Specification
Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s) support with
GTX transceivers
Endpoint and Root Port capable
x1, x2, x4, or x8 lane support per block
Data rates below 480 Mb/s supported by
oversampling in FPGA logic.
Supports 1000BASE-X PCS/PMA and SGMII
using GTX transceivers
Supports MII, GMII, and RGMII using SelectIO
technology resources
2500Mb/s support available

XC6VLX130T-L1FFG484I Summary of contents

  • Page 1

    DS150 (v2.2) January 28, 2010 General Description The Virtex®-6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to ...

  • Page 2

    ... Table 1: Virtex-6 FPGA Feature Summary by Device Configurable Logic Blocks (CLBs) Logic Device Cells Max (1) Slices Distributed RAM (Kb) XC6VLX75T 74,496 11,640 1,045 XC6VLX130T 128,000 20,000 1,740 XC6VLX195T 199,680 31,200 3,040 XC6VLX240T 241,152 37,680 3,650 XC6VLX365T 364,032 56,880 4,130 XC6VLX550T 549,888 85,920 6,200 ...

  • Page 3

    ... Virtex-6 LXT and SXT FPGA package combinations with the maximum available I/Os per package are shown in Table 2: Virtex-6 LXT and SXT FPGA Device-Package Combinations and Maximum Available I/Os FF484 Package FFG484 Size (mm Device GTXs I/O XC6VLX75T 8 240 XC6VLX130T 8 240 XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T Notes: 1. Flip-chip packages are also available in Pb-Free versions (FFG). ...

  • Page 4

    Configuration Virtex-6 FPGAs store their customized configuration in SRAM-type internal latches. The number of configuration bits is between 26 Mb and 160 MB), depending on device size but independent of the specific user-design implementation, unless compression ...

  • Page 5

    Clock Management Each Virtex-6 FPGA has up to nine clock management tiles (CMTs), each consisting of two mixed-mode clock managers (MMCMs), which are PLL based. Phase-Locked Loop The MMCM can serve as a frequency synthesizer for a wider range of ...

  • Page 6

    Block RAM Every Virtex-6 FPGA has between 156 and 1064 dual-port block RAMs, each storing 36 Kbits. Each block RAM has two completely independent ports that share nothing but the stored data. Synchronous Operation Each memory access, read and write, ...

  • Page 7

    Input/Output The number of I/O pins varies from 240 to 1200 depending on device and package size. Each I/O pin is configurable and can comply with a large number of standards, using up to 2.5V. The Virtex-6 FPGA SelectIO Resources ...

  • Page 8

    The System Monitor does not require explicit instantiation in a design. Once the appropriate power supply connections are made, measurement data can be accessed at any time, even pre-configuration or during power down, through the JTAG test access port (TAP). ...

  • Page 9

    This block is highly configurable to system design requirements and can operate lanes at the 2.5 Gb/s data rate and the 5.0 Gb/s data rate. For high-performance applications, advanced buffering techniques of the block offer ...

  • Page 10

    Revision History The following table shows the revision history for this document: Date Version 02/02/09 1.0 Initial Xilinx release. 05/05/09 1.1 Added the FF1156 package for both the XC6VSX315T and XC6VSX475T devices in Updated the PCI Express design discussion on ...

  • Page 11

    Virtex-6 FPGA Documentation Complete and up-to-date documentation of the Virtex-6 family of FPGAs is available on the Xilinx website. In addition to the most recent Virtex-6 Family Overview, the following files are also available for download: Virtex-6 FPGA Data Sheet: ...