LPC2420FET208,551 NXP Semiconductors, LPC2420FET208,551 Datasheet - Page 32

• Manufacturer Part Number: LPC2420FET208,551
• Description: IC ARM7 MCU 16BIT T208FBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2420FET208,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: EBI/EMI, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Type: ROMless
• Ram Size: 82K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-TFBGA
• Processor Series: LPC2420
• Core: ARM7
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: SPI, I2C, I2S, USB, SSP
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Processor To Be Evaluated: ARM7TDMI-S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-5216

NXP Semiconductors
LPC2420_60_5
Preliminary data sheet
7.10.1.1 Features
7.10.1 USB device controller
7.10.2 USB host controller
7.10 USB interface
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The LPC2420/2460 USB interface includes a device, host, and OTG controller. Details on
typical USB interfacing solutions can be found in
solutions” on page 64
The device controller enables 12 Mbit/s data exchange with a USB host controller. It
consists of a register interface, serial interface engine, endpoint buffer memory, and a
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate endpoint buffer. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. When
enabled, the DMA controller transfers data between the endpoint buffer and the USB
RAM.
The host controller enables full- and low-speed data exchange with USB devices attached
to the bus. It consists of register interface, serial interface engine and DMA controller. The
register interface complies with the OHCI specification.
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– Wake-on-LAN power management support allows system wake-up: using the
Physical interface:
– Attachment of external PHY chip through standard MII or RMII interface.
– PHY register access is available via the MIIM interface.
Fully compliant with USB 2.0 specification (full speed).
Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
Supports SoftConnect and GoodLink features.
While USB is in the Suspend mode, LPC2420/2460 can enter one of the reduced
power modes and wake up on USB activity.
Supports DMA transfers with the DMA RAM of 16 kB on all non-control endpoints.
Allows dynamic switching between CPU-controlled and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints.
receive filters or a magic frame detection filter.
Rev. 05 — 24 February 2010
Flashless 16-bit/32-bit microcontroller
Section 13.1 “Suggested USB interface
LPC2420/2460
© NXP B.V. 2010. All rights reserved.
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