MCU PIC 64KB FLASH 28SOIC

PIC18F26K80-I/SO

Manufacturer Part NumberPIC18F26K80-I/SO
DescriptionMCU PIC 64KB FLASH 28SOIC
ManufacturerMicrochip Technology
SeriesPIC® XLP™ 18F
PIC18F26K80-I/SO datasheet
 


Specifications of PIC18F26K80-I/SO

Core Size8-BitProgram Memory Size64KB (32K x 16)
PeripheralsBrown-out Detect/Reset, LVD, POR, PWM, WDTCore ProcessorPIC
Speed64MHzConnectivityECAN, I²C, LIN, SPI, UART/USART
Number Of I /o24Program Memory TypeFLASH
Eeprom Size1K x 8Ram Size3.6K x 8
Voltage - Supply (vcc/vdd)1.8 V ~ 5.5 VData ConvertersA/D 8x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case28-SOIC (0.300", 7.50mm Width)Controller Family/seriesPIC18
Ram Memory Size4KBCpu Speed16MIPS
No. Of Pwm Channels5Embedded Interface TypeI2C, SPI, USART
Processor SeriesPIC18F26K80CorePIC
Data Bus Width8 bitData Ram Size1 KB
Interface TypeI2C, SPI, USARTMaximum Clock Frequency64 MHz
Number Of Programmable I/os24Number Of Timers5
Operating Supply Voltage1.8 V to 5.5 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTLead Free Status / RoHS StatusLead free / RoHS Compliant
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Download datasheet (6Mb)Embed
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PIC18F66K80 Family
Data Sheet
28/40/44/64-Pin, Enhanced Flash
Microcontrollers, with ECAN™
and nanoWatt XLP Technology
Preliminary
 2011 Microchip Technology Inc.
DS39977C

PIC18F26K80-I/SO Summary of contents

  • Page 1

    ... Enhanced Flash  2011 Microchip Technology Inc. PIC18F66K80 Family Microcontrollers, with ECAN™ and nanoWatt XLP Technology Preliminary Data Sheet DS39977C ...

  • Page 2

    ... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

  • Page 3

    ... Three Dedicated Transmit Buffers with Prioritization • Two Dedicated Receive Buffers TABLE 1: DEVICE COMPARISON Data Program Device Memory Memory (Bytes) PIC18F25K80 32 Kbytes 3,648 PIC18LF25K80 32 Kbytes 3,648 PIC18F26K80 64 Kbytes 3,648 PIC18LF26K80 64 Kbytes 3,648 PIC18F45K80 32 Kbytes 3,648 PIC18LF45K80 32 Kbytes 3,648 PIC18F46K80 64 Kbytes 3,648 PIC18LF46K80 64 Kbytes 3,648 ...

  • Page 4

    ... Auto-Baud Detect (ABD) • 12-Bit A/D Converter with Channels: - Auto-acquisition and Sleep operation - Differential Input mode of operation • Data Signal Modulator module: - Select modulator and carrier sources from vari- ous module outputs • Integrated Voltage Reference Preliminary  2011 Microchip Technology Inc. ...

  • Page 5

    ... Pin Diagrams (1) 28-Pin QFN RA2/V REF RA3/V +/AN3 REF V DDCORE RA5/AN4/C2INB/HLVDIN/T1CKI/SS/CTMUI OSC1/CLKIN/RA7 OSC2/CLKOUT/RA6 For the QFN package recommended that the bottom pad be connected to V Note 1:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY -/AN2 PIC18F2XK80 CAP PIC18LF2XK80 Preliminary RB3/CANRX/C2OUT/P1D/CTED2/INT3 RB2/CANTX/C1OUT/P1C/CTED1/INT2 RB1/AN8/C1INB/P1B/CTDIN/INT1 RB0/AN10/C1INA/FLT0/INT0 ...

  • Page 6

    ... RC5/SDO 13 RC4/SDA/SDI RB7/PGD/T3G/KBI3 1 RB6/PGC/KBI2 39 2 RB5/T0CKI/T3CKI/CCP5/KBI1 38 3 RB4/AN9/CTPLS/KBI0 37 4 RB3/CANRX/CTED2/INT3 5 36 RB2/CANTX/CTED1/INT2 6 CAP 35 RB1/AN8/CTDIN/INT1 7 34 RB0/AN10/FLT0/INT0 PIC18F4XK80 PIC18LF4XK80 RD7/RX2/DT2/P1D/PSP7 RD6/TX2/CK2/P1C/PSP6 29 13 RD5/P1B/PSP5 RD4/ECCP1/P1A/PSP4 15 26 RC7/CANRX/RX1/DT1/CCP4 16 RC6/CANTX/TX1/CK1/CCP3 25 17 RC5/SDO 24 18 RC4/SDA/SDI 23 19 RD3/C2INB/CTMUI/PSP3 22 RD2/C2INA/PSP2 21 20 Preliminary  2011 Microchip Technology Inc. ...

  • Page 7

    ... Pin Diagrams (Continued) 44-Pin TQFP RC7/CANRX/RX1/DT1/CCP4 RD4/ECCP1/P1A/PSP4 RD5/P1B/PSP5 RD6/TX2/CK2/P1C/PSP6 RD7/RX2/DT2/P1D/PSP7 RB0/AN10/FLT0/INT0 RB1/AN8/CTDIN/INT1 RB2/CANTX/CTED1/INT2 RB3/CANRX/CTED2/INT3  2011 Microchip Technology Inc. PIC18F66K80 FAMILY PIC18F4XK80 5 29 PIC18LF4XK80 Preliminary N/C RC0/SOSCO/SCLKI OSC2/CLKOUT/RA6 OSC1/CLKIN/RA7 RE2/AN7/C2OUT/CS RE1/AN6/C1OUT/WR RE0/AN5/RD RA5/AN4/HLVDIN/T1CKI/ DDCORE CAP DS39977C-page 7 ...

  • Page 8

    ... RC7/CANRX/RX1/DT1/CCP4 RD4/ECCP1/P1A/PSP4 RD5/P1B/PSP5 RD6/TX2/CK2/P1C/PSP6 RD7/RX2/DT2/P1D/PSP7 RB0/AN10/FLT0/INT0 RB1/AN8/CTDIN/INT1 RB2/CANTX/CTED1/INT2 RB3/CANRX/CTED2/INT3 For the QFN package recommended that the bottom pad be connected to V Note 1: DS39977C-page PIC18F4XK80 5 29 PIC18LF4XK80 Preliminary N/C RC0/SOSCO/SCLKI OSC2/CLKOUT/RA6 OSC1/CLKIN/RA7 RE2/AN7/C2OUT/CS RE1/AN6/C1OUT/WR RE0/AN5/RD RA5/AN4/HLVDIN/T1CKI/ DDCORE CAP . SS  2011 Microchip Technology Inc. ...

  • Page 9

    ... RD7/P1D/PSP7 5 RG0/RX1/DT1 6 RG1/CANTX2 RG2/T3CKI 11 RG3/TX1/CK1 12 RB0/AN10/FLT0/INT0 13 14 RB1/AN8/CTDIN/INT1 RB2/CANTX/CTED1/INT2 15 RB3/CANRX/CTED2/INT3 16 For the QFN package recommended that the bottom pad be connected to V Note 1:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY RC0/SOSCO/SCLKI 48 OSC2/CLKOUT/RA6 47 OSC1/CLKIN/RA7 46 RF5 45 RF4/MDCIN2 VSS V PIC18F6XK80 VDD 40 PIC18LF6XK80 RE2/AN7/C2OUT/CS 39 RE1/AN6/C1OUT/WR 38 RE0/AN5/RD ...

  • Page 10

    ... Packaging Information.............................................................................................................................................................. 589 Appendix A: Revision History............................................................................................................................................................. 609 Appendix B: Migration to PIC18F66K80 Family................................................................................................................................. 609 Index ................................................................................................................................................................................................. 611 The Microchip Web Site ..................................................................................................................................................................... 625 Customer Change Notification Service .............................................................................................................................................. 625 Customer Support .............................................................................................................................................................................. 625 Reader Response .............................................................................................................................................................................. 626 Product Identification System............................................................................................................................................................. 627 DS39977C-page 10 Preliminary  2011 Microchip Technology Inc. ...

  • Page 11

    ... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Preliminary DS39977C-page 11 ...

  • Page 12

    ... PIC18F66K80 FAMILY NOTES: DS39977C-page 12 Preliminary  2011 Microchip Technology Inc. ...

  • Page 13

    ... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F25K80 • PIC18LF25K80 • PIC18F26K80 • PIC18LF26K80 • PIC18F45K80 • PIC18LF45K80 • PIC18F46K80 • PIC18LF46K80 • PIC18F65K80 • PIC18LF65K80 • PIC18F66K80 • PIC18LF66K80 This family combines the traditional advantages of all PIC18 microcontrollers – ...

  • Page 14

    ... The devices are differentiated from each other in these ways: • Flash Program Memory: - PIC18FX5K80 (PIC18F25K80, PIC18F45K80 and PIC18F45K80) – 32 Kbytes - PIC18FX6K80 (PIC18F26K80, PIC18F46K80 and PIC18F66K80) – 64 Kbytes • I/O Ports: - PIC18F2XK80 (28-pin devices) – Three bidirectional ports - PIC18F4XK80 (40/44-pin devices) – Five bidirectional ports - PIC18F6XK80 (64-pin devices) – ...

  • Page 15

    ... One MSSP and Two Enhanced USARTs (EUSART) Eleven Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled 40-Pin PDIP and 44-Pin QFN and TQFP Preliminary PIC18F26K80 64K 32,768 PIC18F46K80 64K 32,768 DS39977C-page 15 ...

  • Page 16

    ... One MSSP and Two Enhanced USARTs (EUSART) Eleven Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled 64-Pin QFN and TQFP Preliminary PIC18F66K80 64K 32,768 Yes  2011 Microchip Technology Inc. ...

  • Page 17

    ... Note 1: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see 2: Configurations”. RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0). 3:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Data Bus<8> Data Latch 8 8 Data Memory ...

  • Page 18

    ... Timer BOR and LVD , V MCLR SS ADC Timer3 CTMU 12-Bit MSSP ECAN EUSART2 Preliminary PORTA RA0:RA3 RA5:RA7 (1,2) 12 PORTB (1) RB0:RB7 12 4 Access Bank 12 PORTC (1) RC0:RC7 PORTD (1) RD0:RD7 8 PORTE PRODL (1,3) RE0:RE3 Comparator 1/2 PSP Section 3.0 “Oscillator  2011 Microchip Technology Inc. ...

  • Page 19

    ... Note 1: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see 2: Configurations”. RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0). 3:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Data Bus<8> Data Latch 8 8 Data Memory ...

  • Page 20

    ... In certain oscillator modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O ST/ General purpose I/O pin. CMOS C™ C/SMBus input buffer Analog = Analog input O = Output Preliminary Description  2011 Microchip Technology Inc. ...

  • Page 21

    ... C2INB HLVDIN T1CKI SS CTMUI Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input P = Power  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O ST/ General purpose I/O pin. CMOS O Analog Comparator reference voltage output. ...

  • Page 22

    ... I ST CTMU Edge 1 input External Interrupt 2. I/O ST/ Digital I/O. CMOS I ST CAN bus RX. O CMOS Comparator 2 output. O CMOS Enhanced PWM1 Output CTMU Edge 2 input External Interrupt C™ C/SMBus input buffer Analog = Analog input O = Output Preliminary Description  2011 Microchip Technology Inc. ...

  • Page 23

    ... RB7 PGD T3G RX2 DT2 KBI3 Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input P = Power  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Pin Buffer Type Type I/O ST/ Digital I/O. CMOS I Analog Analog Input 9. I Analog Comparator 2 Input A. ...

  • Page 24

    ... Digital I/O. CMOS O CMOS CAN bus TX. O CMOS EUSART asynchronous transmit. I/O ST EUSART synchronous clock. (See related RX1/DT1.) I/O ST/ Capture 3 input/Compare 3 output/PWM3 output. CMOS C™ C/SMBus input buffer Analog = Analog input O = Output Preliminary Description 2 C mode.  2011 Microchip Technology Inc. ...

  • Page 25

    ... CAP V DDCORE V CAP Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input P = Power  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Pin Buffer Type Type I/O ST/ Digital I/O. CMOS I ST CAN bus RX EUSART asynchronous receive. I/O ST EUSART synchronous data (see related TX2/CK2). ...

  • Page 26

    ... In certain oscillator modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O ST/ General purpose I/O pin. CMOS CMOS = CMOS compatible input or output Analog = Analog input O = Output Preliminary Description  2011 Microchip Technology Inc. ...

  • Page 27

    ... Legend: I C™ C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O ST/ General purpose I/O pin. CMOS O Analog Comparator reference voltage output. ...

  • Page 28

    ... CTMU pulse generator output Interrupt-on-change pin. I/O ST/ Digital I/O. CMOS I ST Timer0 external clock input Timer3 external clock input. I/O ST Capture 5 input/Compare 5 output/PWM5 output Interrupt-on-change pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output Preliminary Description  2011 Microchip Technology Inc. ...

  • Page 29

    ... T3G KBI3 2 2 Legend: I C™ C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Pin Buffer Type Type I/O ST/ Digital I/O. CMOS I ST In-Circuit Debugger and ICSP™ programming clock input pin ...

  • Page 30

    ... Digital I/O. CMOS O CMOS CAN bus TX. O CMOS EUSART synchronous transmit. I/O ST EUSART synchronous clock (see related RX2/DT2). I/O ST Capture 3 input/Compare 3 output/PWM3 output. CMOS = CMOS compatible input or output Analog = Analog input O = Output Preliminary Description 2 C mode.  2011 Microchip Technology Inc. ...

  • Page 31

    ... RC7 CANRX RX1 DT1 CCP4 2 2 Legend: I C™ C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Pin Buffer Type Type I/O ST/ Digital I/O. CMOS I ST CAN bus RX EUSART asynchronous receive. ...

  • Page 32

    ... Capture 1 input/Compare 1 output/PWM1 output. O CMOS Enhanced PWM1 Output A. I/O ST/ Parallel Slave Port data. CMOS I/O ST/ Digital I/O. CMOS O CMOS Enhanced PWM1 Output B. I/O ST/ Parallel Slave Port data. CMOS CMOS = CMOS compatible input or output Analog = Analog input O = Output Preliminary Description  2011 Microchip Technology Inc. ...

  • Page 33

    ... AN7 C2OUT CS RE3 2 2 Legend: I C™ C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Pin Buffer Type Type I/O ST/ Digital I/O. CMOS I ST EUSART asynchronous transmit. I/O ST EUSART synchronous clock (see related RX2/DT2). ...

  • Page 34

    ... Ground reference for logic and I/O pins. P External filter capacitor connection External filter capacitor connection P Positive supply for logic and I/O pins. P Positive supply for logic and I/O pins. CMOS = CMOS compatible input or output Analog = Analog input O = Output Preliminary Description  2011 Microchip Technology Inc. ...

  • Page 35

    ... Legend: I C™ C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Buffer Description Type ST Master Clear (input) or programming voltage (input).This pin is an active-low Reset to the device. ST General purpose, input only pin. ...

  • Page 36

    ... Analog A/D reference voltage (high) input. Analog Analog Input 3. ST/ Digital I/O. CMOS Analog Analog Input 4. Analog High/Low-Voltage Detect input. ST Timer1 clock input. ST SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output Preliminary  2011 Microchip Technology Inc. ...

  • Page 37

    ... Legend: I C™ C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Buffer Description Type PORTB is a bidirectional I/O port. ST/ Digital I/O. CMOS Analog Analog Input 10. ST Enhanced PWM Fault input for ECCP1. ...

  • Page 38

    ... In-Circuit Debugger and ICSP™ programming clock input pin. ST Interrupt-on-change pin. ST/ Digital I/O. CMOS ST In-Circuit Debugger and ICSP™ programming data pin. ST Timer3 external clock gate input. ST Interrupt-on-change pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output Preliminary  2011 Microchip Technology Inc. ...

  • Page 39

    ... I/O CCP4 I Legend: I C™ C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Buffer Description Type PORTC is a bidirectional I/O port. ST/ Digital I/O. CMOS ST Timer1 oscillator output. ST Digital SOSC input. ST/ Digital I/O ...

  • Page 40

    ... Capture 1 input/Compare 1 output/PWM1 output. CMOS Enhanced PWM1 Output A. ST/ Parallel Slave Port data. CMOS ST/ Digital I/O. CMOS CMOS Enhanced PWM1 Output B. ST/ Parallel Slave Port data. CMOS CMOS = CMOS compatible input or output Analog = Analog input O = Output Preliminary  2011 Microchip Technology Inc. ...

  • Page 41

    ... O PSP7 I Legend: I C™ C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Buffer Description Type ST/ Digital I/O. CMOS CMOS Enhanced PWM1 Output C. ST/ Parallel Slave Port data. CMOS ST/ Digital I/O. CMOS CMOS Enhanced PWM1 Output D ...

  • Page 42

    ... CMOS CAN bus TX. ST/ Digital I/O. CMOS ST EUSART asynchronous receive. ST EUSART synchronous data (see related TX2/CK2). ST/ Digital I/O. CMOS CMOS EUSART asynchronous transmit. ST EUSART synchronous clock (see related RX2/DT2). CMOS = CMOS compatible input or output Analog = Analog input O = Output Preliminary  2011 Microchip Technology Inc. ...

  • Page 43

    ... RF7 I Legend: I C™ C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Buffer Description Type PORTF is a bidirectional I/O port. ST/ Digital I/O. CMOS CMOS Modulator source input. ST/ Digital I/O. CMOS ST/ Digital I/O ...

  • Page 44

    ... Digital I/O. CMOS ST Timer3 clock input. ST/ Digital I/O. CMOS CMOS EUSART asynchronous transmit. ST EUSART synchronous clock (see related RX2/DT2). ST/ Digital I/O. CMOS ST Timer0 external clock input. CMOS = CMOS compatible input or output Analog = Analog input O = Output Preliminary  2011 Microchip Technology Inc. ...

  • Page 45

    ... Legend: I C™ C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels I = Input P = Power  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Buffer Description Type P Ground reference for logic and I/O pins. P Ground reference for logic and I/O pins. P Ground reference for analog modules. ...

  • Page 46

    ... PIC18F66K80 FAMILY NOTES: DS39977C-page 46 Preliminary  2011 Microchip Technology Inc. ...

  • Page 47

    ... REF REF reference for analog modules is implemented The AV and AV pins must always be Note connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 2- MCLR ( Pin” ...

  • Page 48

    ... The DD may be beneficial. A typical Figure 2-1. Other circuit ) and fast signal transitions must IL (Figure 2-2). is replaced for normal run-time EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC18FXXKXX JP C1 and V specifications are met and V specifications are met. IL  2011 Microchip Technology Inc. ...

  • Page 49

    ... These devices require a 10 F capacitor on the V /V pin. CAP DDCORE For details on all members of the PIC18F66K80 family, see Section 28.3 “On-Chip Voltage Regulator”.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 2- 0.1 to evaluate 0.01 0.001 0.01 Typical data measurement at 25° bias. ...

  • Page 50

    ... In all cases, the guard trace(s) must be returned to ground. Preliminary 16V -55 to 125ºC 16V -55 to 85ºC 16V -55 to 125ºC 16V -55 to 85ºC 16V -55 to 125ºC 16V -55 to 85ºC  2011 Microchip Technology Inc. ...

  • Page 51

    ... Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ kΩ resistor unused pins and drive the SS output to logic low.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 2-4: Single-Sided and In-Line Layouts: Copper Pour (tied to ground) Devices” ...

  • Page 52

    ... PIC18F66K80 FAMILY NOTES: DS39977C-page 52 Preliminary  2011 Microchip Technology Inc. ...

  • Page 53

    ... When the RA6 and RA7 pins are not used for an oscil- lator function or CLKOUT function, they are available as general purpose I/Os.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY To optimize power consumption when using EC/HS/ XT/LP/RC as the primary oscillator, the frequency input ...

  • Page 54

    ... INTSRC MFIOSEL Preliminary FOSC<3:0> Setting 1101 1100 1011 1010 0101 0100 0011 0010 0001 0000 001x 100x (and OSCCON, OSCCON2) Peripherals CPU IDLEN Clock Control SCS<1:0> FOSC<3:0> IRCF<2:0>  2011 Microchip Technology Inc. ...

  • Page 55

    ... INTSRC = OSCTUNE<7> and MFIOSEL = OSCCON2<0>. 5: Lowest power option for an internal source. 6:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY The OSCTUNE register tuning and operation of the internal oscillator block. It also implements the PLLEN bit which controls the operation of the Phase Locked Loop (PLL) (see Frequency Multiplier” ...

  • Page 56

    ... When SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no Note 1: effect. DS39977C-page 56 (4) R/W-0 R/W-0 U-0 (1) SOSCDRV SOSCGO — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R-x R/W-0 MFIOFS MFIOSEL bit Bit is unknown  2011 Microchip Technology Inc. ...

  • Page 57

    ... Center frequency; fast RC oscillator is running at the calibrated frequency 111111 • • • • 100000 = Minimum frequency  2011 Microchip Technology Inc. PIC18F66K80 FAMILY R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...

  • Page 58

    ... Sleep mode or one of the Idle modes when the SLEEP instruction is executed. Preliminary Design Operating Frequency 31.25-100 kHz 100 kHz to 4 MHz 4 MHz to 25 MHz MHz (external clock MHz (external RC) Select bits, SCS<1:0> and SOSCRUN  2011 Microchip Technology Inc. ...

  • Page 59

    ... This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 4.1.2 “Entering Power-Managed  2011 Microchip Technology Inc. PIC18F66K80 FAMILY 3.4 RC Oscillator Section 4.0 For timing-insensitive applications, the RC and RCIO Oscillator modes offer additional cost savings ...

  • Page 60

    ... DD CRYSTAL/CERAMIC RESONATOR OPERATION (HS OR HSPLL CONFIGURATION) OSC1 To Internal Logic XTAL ( Sleep OSC2 PIC18F66K80 ( Table 3-2 and Table 3-3 for initial values of ) may be required for AT S varies with the oscillator mode chosen.  2011 Microchip Technology Inc. ...

  • Page 61

    ... This may be useful for customers who are concerned with EMI due to high-frequency crystals or users who require higher clock speeds from an internal oscillator.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY 3.5.3.1 HSPLL and ECPLL Modes The HSPLL and ECPLL modes provide the ability to ...

  • Page 62

    ... In INTPLL2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output. Externally, this is identical to INTIO2 (Figure 3-9). 3-9). Both Preliminary INTIO1 OSCILLATOR MODE I/O (OSC1) PIC18F66K80 OSC2 INTIO2 OSCILLATOR MODE I/O (OSC1) PIC18F66K80 I/O (OSC2) /4, OSC 3-8).  2011 Microchip Technology Inc. ...

  • Page 63

    ... If the internally clocked timer value is much greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY 3.6.4.3 Compensating with the CCP Module in Capture Mode ...

  • Page 64

    ... For ROSEL (REFOCON<4>), the primary oscillator is available only when configured as the default via the Note 1: FOSC settings. This is regardless of whether the device is in Sleep mode. DS39977C-page 64 R/W-0 R/W-0 R/W-0 (1) ROSEL RODIV3 RODIV2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 RODIV1 RODIV0 bit Bit is unknown  2011 Microchip Technology Inc. ...

  • Page 65

    ... INTOSC, INTPLL1/2 I/O pin, RA6, direction controlled by TRISA<6> See Note: Section 5.0 “Reset”  2011 Microchip Technology Inc. PIC18F66K80 FAMILY 3.9 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applica- tions. The delays ensure that the device is kept in ...

  • Page 66

    ... PIC18F66K80 FAMILY NOTES: DS39977C-page 66 Preliminary  2011 Microchip Technology Inc. ...

  • Page 67

    ... Note 1: Includes INTOSC (HF-INTOSC and MG-INTOSC) and INTOSC postscaler, as well as the LF-INTOSC 2: source.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS<1:0> bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock ...

  • Page 68

    ... SOSCRUN bit is cleared, the OSTS bit is set and the . Improper DD primary clock is providing the clock. The IDLEN and / DD SCS bits are not affected by the wake-up and the SOSC oscillator continues to run. Preliminary Section 28.4 “Two-Speed Registers”.) Figure 4-1), the primary oscillator  2011 Microchip Technology Inc. ...

  • Page 69

    ... HF-INTOSC) – there are no distinguishable differences between the PRI_RUN and RC_RUN modes during execution. Entering or exiting RC_RUN mode, how- ever, causes a clock switch delay. Therefore, if the primary clock source is the internal oscillator block, using RC_RUN mode is not recommended.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY n-1 ...

  • Page 70

    ... OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The LF-INTOSC source will continue to run if either the WDT or the Fail-Safe Clock Monitor (FSCM) is enabled. Preliminary Figure 4-4). When the clock  2011 Microchip Technology Inc. ...

  • Page 71

    ... PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS<1:0> Bits Changed Note1 1024 (approx). These intervals are not shown to scale. OST OSC PLL 2: Clock transition typically occurs within 2-4 T  2011 Microchip Technology Inc. PIC18F66K80 FAMILY n-1 n (1) Clock Transition OSC ...

  • Page 72

    ... IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or Sleep mode, a WDT time- out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits (1) PLL OSTS Bit Set Preliminary CSD 31-11) while it becomes ready  2011 Microchip Technology Inc. ...

  • Page 73

    ... OSC1 CPU Clock Peripheral Clock Program Counter Wake Event  2011 Microchip Technology Inc. PIC18F66K80 FAMILY 4.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the SOSC oscillator. This mode is entered from SEC_RUN by set- ting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS< ...

  • Page 74

    ... Many peripheral modules have a corresponding PMD bit. There are three PMD registers in PIC18F66K80 family devices: PMD0, PMD1 and PMD2. These registers have bits associated with each module for disabling or enabling a particular peripheral. Preliminary  2011 Microchip Technology Inc. eliminating their power ...

  • Page 75

    ... CMP1MD: Comparator 1 Module Disable bit 1 = The Comparator 1 module is disabled. All Comparator 1 registers are held in Reset and are not writable The Comparator 1 module is enabled Only implemented on devices with 64 pins (PIC18F6XK80, PIC18LF6XK80). Note 1:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY U-0 R/W-0 R/W-0 — ...

  • Page 76

    ... The Timer0 module is enabled Unimplemented on devices with 28-pin devices (PIC18F2XK80, PIC18LF2XK80). Note 1: DS39977C-page 76 R/W-0 R/W-0 R/W-0 TMR4MD TMR3MD TMR2MD U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 TMR1MD TMR0MD bit Bit is unknown  2011 Microchip Technology Inc. ...

  • Page 77

    ... The USART1 module is disabled. All USART1 registers are held in Reset and are not writable The USART1 module is enabled bit 0 SSPMD: MSSP Module Disable bit 1 = The MSSP module is disabled. All SSP registers are held in Reset and are not writable The MSSP module is enabled  2011 Microchip Technology Inc. PIC18F66K80 FAMILY R/W-0 R/W-0 R/W-0 CCP2MD ...

  • Page 78

    ... CSD leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. Preliminary 4-4. Start-up”) or Fail-Safe Section 28.5 “Fail-Safe Clock  2011 Microchip Technology Inc. ...

  • Page 79

    ... WDTCONbits.ULPSINK = 1; //For Sleep OSCCONbits.IDLEN = 0; //Enter Sleep Mode // Sleep(); //for sleep, execution will //resume here  2011 Microchip Technology Inc. PIC18F66K80 FAMILY A series resistor, between RA0 and the external capacitor, provides overcurrent protection for the RA0/ CV /AN0/ULPWU REF calibration of the time-out (see ...

  • Page 80

    ... Section 4.4 “Idle Modes” Table 31-11 PLL (Parameter 39, Table 31-11), the INTOSC stabilization period. IOBST Preliminary Clock Ready Status Bits OSTS (1) HFIOFS MFIOFS None (1) SOSCRUN HFIOFS (1) MFIOFS None (3) ( OSTS rc (1) HFIOFS (4) MFIOFS None ). is the PLL Lock-out Timer RC  2011 Microchip Technology Inc. ...

  • Page 81

    ... Ripple Counter Note 1: This is the INTOSC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 5-2 for time-out situations.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1 ...

  • Page 82

    ... Brown-out Reset is said to have occurred when BOR is ‘ 0 ’ and POR is ‘ 1 ’ (assuming that POR was set to ‘ 1 ’ by software immediately after a Power-on Reset). DS39977C-page 82 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) for additional information. Preliminary (2) R/W-0 R/W-0 POR BOR bit Bit is unknown  2011 Microchip Technology Inc. ...

  • Page 83

    ... Reset occurs; it does not change for any other Reset event. POR is not reset to ‘ 1 ’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘ 1 ’ in software following any Power-on Reset.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 5-2: V ...

  • Page 84

    ... BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes; disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. Preliminary and operates as previously  2011 Microchip Technology Inc. ...

  • Page 85

    ... Resets. As with all hard and power Reset events, the device Configuration Words are reloaded from the Flash Configuration Words in program memory as the device restarts.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY 5.6 Device Reset Timers PIC18F66K80 family devices incorporate three sepa- ...

  • Page 86

    ... OSC OSC (1) — (1) — (1) — T PWRT T OST Preliminary Figure 5-3, 5-5, Figure 5-6 and Figure 5-7 all 5-3 through 5-6 also apply Exit from Power-Managed Mode (2) (2) 1024 OSC 1024 T OSC — — — RISE < PWRT  2011 Microchip Technology Inc. ...

  • Page 87

    ... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET  2011 Microchip Technology Inc. PIC18F66K80 FAMILY T PWRT T OST T PWRT T OST , V RISE > ...

  • Page 88

    ... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET T = 1024 clock cycles. Note: OST  max. First three stages of the PWRT timer. T PLL DS39977C-page 88 T PWRT T OST T PLL Preliminary  2011 Microchip Technology Inc ...

  • Page 89

    ... Reset state is ‘ 1 ’ for POR and unchanged for all other Resets when software BOR is enabled 2: (BOREN<1:0> Configuration bits = 01 and SBOREN = 1 ); otherwise, the Reset state is ‘ 0 ’.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY ferent Reset situations, as indicated in These bits are used in software to determine the nature of the Reset ...

  • Page 90

    ... N/A PIC18F6XK80 N/A PIC18F6XK80 N/A PIC18F6XK80 ---- xxxx ---- uuuu PIC18F6XK80 xxxx xxxx uuuu uuuu PIC18F6XK80 ---- 0000 ---- 0000 PIC18F6XK80 N/A Preliminary  2011 Microchip Technology Inc. Wake-up via WDT or Interrupt (3) ---0 uuuu (3) uuuu uuuu (3) uuuu uuuu (3) uu-u uuuu ---u uuuu uuuu uuuu ( --uu uuuu uuuu uuuu ...

  • Page 91

    ... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not 5: enabled as PORTA pins, they are disabled and read ‘0’. This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 6:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Power-on MCLR Resets, Reset, ...

  • Page 92

    ... PIC18F6XK80 0000 0000 0000 0000 PIC18F6XK80 -000 0000 -000 0000 PIC18F6XK80 00-0 0001 xx-x xxxx Preliminary  2011 Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu uuuu u-uu uuuu -uuu uuuu -uuu uuuu -uuu uuuu uuuu uu-- ---- ...

  • Page 93

    ... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not 5: enabled as PORTA pins, they are disabled and read ‘0’. This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 6:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Power-on MCLR Resets, Reset, ...

  • Page 94

    ... PIC18F6XK80 1111 1111 1111 1111 PIC18F6XK80 1111 ---- 1111 ---- PIC18F6XK80 0000 0000 0000 0000 Preliminary  2011 Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- --00 uuuu uuuu uuuu uuuu uuuu uuuu ...

  • Page 95

    ... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not 5: enabled as PORTA pins, they are disabled and read ‘0’. This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 6:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Power-on MCLR Resets, Reset, ...

  • Page 96

    ... PIC18F6XK80 -x-- xxxx -u-- uuuu PIC18F6XK80 xxxx xxxx uuuu uuuu PIC18F6XK80 xxxx xxxx uuuu uuuu Preliminary  2011 Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ...

  • Page 97

    ... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not 5: enabled as PORTA pins, they are disabled and read ‘0’. This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 6:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Power-on MCLR Resets, Reset, ...

  • Page 98

    ... PIC18F6XK80 xxxx xxxx uuuu uuuu PIC18F6XK80 0000 0000 0000 0000 PIC18F6XK80 1000 0000 1000 0000 Preliminary  2011 Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu ...

  • Page 99

    ... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not 5: enabled as PORTA pins, they are disabled and read ‘0’. This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 6:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Power-on MCLR Resets, Reset, ...

  • Page 100

    ... PIC18F6XK80 xxxx xxxx uuuu uuuu PIC18F6XK80 xxxx xxxx uuuu uuuu PIC18F6XK80 xxxx xxxx uuuu uuuu Preliminary  2011 Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu ...

  • Page 101

    ... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not 5: enabled as PORTA pins, they are disabled and read ‘0’. This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 6:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Power-on MCLR Resets, Reset, ...

  • Page 102

    ... PIC18F6XK80 0000 0000 0000 0000 PIC18F6XK80 0000 0000 0000 0000 PIC18F6XK80 00-- -000 00-- -000 Preliminary  2011 Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu ...

  • Page 103

    ... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not 5: enabled as PORTA pins, they are disabled and read ‘0’. This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 6:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Power-on MCLR Resets, Reset, ...

  • Page 104

    ... PIC18F66K80 FAMILY NOTES: DS39977C-page 104 Preliminary  2011 Microchip Technology Inc. ...

  • Page 105

    ... Unimplemented Read as ‘0’ Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. Note:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY The data EEPROM, for practical purposes, can be regarded as a peripheral device because it is addressed and accessed through a set of control registers ...

  • Page 106

    ... PIC18F25K80, PIC18F45K80 and PIC18F65K80 – 32 Kbytes of Flash memory, storing up to 16,384 single-word instructions • PIC18F26K80, PIC18F46K80 and PIC18F66K80 – 64 Kbytes of Flash memory, storing up to 32,768 single-word instructions The program memory maps for individual family members are shown in Figure 6-1 ...

  • Page 107

    ... TOSH TOSL 00h 1Ah 34h  2011 Microchip Technology Inc. PIC18F66K80 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack (TOS) Special Function Registers ...

  • Page 108

    ... TOS value. R/W-0 R/W-0 R/W-0 SP4 SP3 SP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary and Instructions POP R/W-0 R/W-0 SP1 SP0 bit Bit is unknown  2011 Microchip Technology Inc. ...

  • Page 109

    ... SUB1  RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK  2011 Microchip Technology Inc. PIC18F66K80 FAMILY 6.1.5 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...

  • Page 110

    ... Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Execute INST (PC) Fetch INST ( Execute INST ( Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Preliminary 6-3 Internal Phase Clock Fetch INST ( Flush ( NOP ) Fetch SUB_1 Execute SUB_1  2011 Microchip Technology Inc. ...

  • Page 111

    ... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF  2011 Microchip Technology Inc. PIC18F66K80 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...

  • Page 112

    ... When this instruction executes, it ignores the BSR completely. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. Preliminary 6-7.  2011 Microchip Technology Inc. ...

  • Page 113

    ... Addresses, E41h through F5Fh, are also used by SFRs, but are not part of the Access RAM. Note 1: Users must always use the complete address, or load the proper BSR value, to access these registers.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Data Memory Map 000h ...

  • Page 114

    ... This is data RAM which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. Preliminary (2) From Opcode  2011 Microchip Technology Inc. ...

  • Page 115

    ... Addresses, E41h through F5Fh, are also used by the SFRs, but are not part of the Access RAM. To access these registers, users must 5: always load the proper BSR value.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY The SFRs can be classified into two sets: those associated with the “ ...

  • Page 116

    ... E5Bh RXF10EIDL (5) E5Ah RXF10EIDH (5) E59h RXF10SIDL E58h RXF10SIDH (5) (5) E57h RXF9EIDL (5) E56h RXF9EIDH (5) E55h RXF9SIDL (5) (5) E54h RXF9SIDH (5) (5) E53h RXF8EIDL (5) E52h RXF8EIDH (5) (5) (5) E51h RXF8SIDL (5) (5) E50h RXF8SIDH (5)  2011 Microchip Technology Inc. (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) ...

  • Page 117

    ... OSCCON IDLEN IRCF2 FD2h OSCCON2 — SOSCRUN FD1h WDTCON REGSLP — FD0h RCON IPEN SBOREN  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 — Top-of-Stack Upper Byte (TOS<20:16>) — SP4 SP3 SP2 Bit 21 Holding Register for PC<20:16> Bit 21 Program Memory Table Pointer Upper Byte (TBLPTR< ...

  • Page 118

    ... CCP3IE 92 CVR1 CVR0 92 — — — RD16 TMR3ON 92 T3GSS1 T3GSS0 TRMT TX9D 92 OERR RX9D 92 T1GSS1 T1GSS0 92 92 HLVDL1 HLVDL0 92 — WUE ABDEN 92 OERR RX9D 92 CCP1IP — 92 CCP1IF — 92 CCP1IE — 92 TMR3IP TMR3GIP 92 TMR3IF TMR3GIF 92 TMR3IE TMR3GIE 92  2011 Microchip Technology Inc. ...

  • Page 119

    ... MDSEL1 MDSEL0 F71h COMSTAT RXB0OVFL RXB1OVFL F70h CIOCON TX2SRC TX2EN F6Fh CANCON REQOP2 REQOP1 F6Eh CANSTAT OPMODE2 OPMODE1  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RC1IP TX1IP SSPIP TMR1GIP RC1IF TX1IF SSPIF TMR1GIF RC1IE TX1IE SSPIE TMR1GIE — ...

  • Page 120

    ... SSPMD 94 TMR1MD TMR0MD 95 CMP2MD CMP1MD 95 — CTMUDS 95 IDISSEN CTTRIG 95 95 IRNG1 IRNG0 CCP2M1 CCP2M0 CCP3M1 CCP3M0 CCP4M1 CCP4M0 CCP5M1 CCP5M0 95 — — 95 — MDBIT 95 MDSRC1 MDSRC0 95 MDCH1 MDCH0 95 MDCL1 MDCL0 95 — — RXB1D71 RXB1D70 95 RXB1D61 RXB1D60 95  2011 Microchip Technology Inc. ...

  • Page 121

    ... CANSTAT_RO3 CANSTAT_RO3 F0Dh TXB2D7 TXB2D77 TXB2D76 F0Ch TXB2D6 TXB2D67 TXB2D66 F0Bh TXB2D5 TXB2D57 TXB2D56 F0Ah TXB2D4 TXB2D47 TXB2D46  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RXB1D55 RXB1D54 RXB1D53 RXB1D52 RXB1D45 RXB1D44 RXB1D43 RXB1D42 RXB1D35 RXB1D34 RXB1D33 RXB1D32 ...

  • Page 122

    ... EID9 EID8 98 EID17 EID16 98 SID4 SID3 98 EID1 EID0 98 EID9 EID8 98 EID17 EID16 98 SID4 SID3 98 EID1 EID0 98 EID9 EID8 98 EID17 EID16 98 SID4 SID3 B5D71 B5D70 98 B5D61 B5D60 98 B5D51 B5D50 98 B5D41 B5D40 98 B5D31 B5D30 98 B5D21 B5D20 98 B5D11 B5D10 98  2011 Microchip Technology Inc. ...

  • Page 123

    ... B2D27 B2D26 EA7h B2D1 B2D17 B2D16 EA6h B2D0 B2D07 B2D06 EA5h B2DLC — TXRTR EA4h B2EIDL EID7 EID6  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 B5D05 B5D04 B5D03 B5D02 — — DLC3 DLC2 EID5 EID4 EID3 EID2 ...

  • Page 124

    ... EID1 EID0 101 EID9 EID8 101 EID17 EID16 101 SID4 SID3 101 TXPRI1 TXPRI0 101 FILHIT1 FILHIT0 101 — — 101 101 — — 101 101 101 101 101 101 101 101 101 101 101  2011 Microchip Technology Inc. ...

  • Page 125

    ... TABLE 6-2: PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED) Addr. File Name Bit 7 Bit 6 E72h RXFBCON1 CAN Buffer 3/2 Pointer Register  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 Preliminary Value on Bit 1 Bit 0 POR, BOR on page 101 DS39977C-page 125 ...

  • Page 126

    ... EID17 EID16 102 SID4 SID3 102 EID1 EID0 102 EID9 EID8 102 EID17 EID16 102 SID4 SID3 102 102 102 SEG2PH1 SEG2PH0 102 PRSEG1 PRSEG0 103 BRP1 BRP0 103 TEC1 TEC0 103 REC1 REC0 103  2011 Microchip Technology Inc. ...

  • Page 127

    ... For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second 2: operand. For rotate ( RRF, RLF ) instructions, this bit is loaded with either the high or low-order bit of the source register.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions be used to ...

  • Page 128

    ... It also enables users to perform and other Stack Pointer HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING FSR0, 100h ; POSTINC0 ; Clear INDF ; register then ; inc pointer FSR0H All done with ; Bank1? NEXT ; NO, clear next ; YES, continue  2011 Microchip Technology Inc. ...

  • Page 129

    ... FCCh. This means the contents of location FCCh will be added to that of the W register and stored back in FCCh.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY mapped in the SFR space, but are not physically imple- mented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. ...

  • Page 130

    ... Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. Preliminary  2011 Microchip Technology Inc. ...

  • Page 131

    ... Enabling the extended instruction set adds five additional two-word commands to the existing PIC18 instruction set: ADDFSR , CALLW , MOVSF , MOVSS and SUBFSR . These instructions are executed as described in Section 6.2.4 “Two-Word Instructions”  2011 Microchip Technology Inc. PIC18F66K80 FAMILY . Preliminary DS39977C-page 131 ...

  • Page 132

    ... Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in “Extended Instruction Syntax” Preliminary  2011 Microchip Technology Inc. Figure 6-9. Section 29.2.1 . ...

  • Page 133

    ... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY 000h 060h Bank 0 100h Bank 1 through ...

  • Page 134

    ... BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. Not Accessible Bank 0 Window Bank 1 Bank 2 through Bank 14 Bank 15 SFRs Data Memory Preliminary 00h Bank 1 “Window” 5Fh 60h SFRs FFh Access Bank  2011 Microchip Technology Inc. ...

  • Page 135

    ... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...

  • Page 136

    ... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. The EEIF interrupt flag bit (PIR4<6>) is Note: set when the write is complete. It must be cleared in software. Preliminary Table Latch (8-bit) TABLAT  2011 Microchip Technology Inc. ...

  • Page 137

    ... RD bit cannot be set when EEPGD = 1 or CFGS = Does not initiate an EEPROM read When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error Note 1: condition.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY R/W-0 R/W-x R/W-0 ...

  • Page 138

    ... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TBLPTR<21:6> TABLE READ – TBLPTR<21:0> Preliminary . TBLPTRL 0 TABLE WRITE TBLPTR<5:0>  2011 Microchip Technology Inc. ...

  • Page 139

    ... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVF WORD_ODD  2011 Microchip Technology Inc. PIC18F66K80 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...

  • Page 140

    ... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary  2011 Microchip Technology Inc. ...

  • Page 141

    ... Clear the CFGS bit to access program memory • Set the WREN to enable byte writes 8. Disable the interrupts.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device ...

  • Page 142

    ... TBLWT holding register. ; loop until buffers are full Preliminary  2011 Microchip Technology Inc. ...

  • Page 143

    ... EEIE Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used during Flash/EEPROM access. Bit 21 of the TBLPTRU allows access to the device Configuration bits. Note 1:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY ; point to Flash program memory ; access Flash program memory ...

  • Page 144

    ... PIC18F66K80 FAMILY NOTES: DS39977C-page 144 Preliminary  2011 Microchip Technology Inc. ...

  • Page 145

    ... EEPROM for read and write operations. EEADRH holds the two MSbs of the address; the upper 6 bits are ignored. The 10-bit range of the pair can address a memory range of 1024 bytes (00h to 3FFh).  2011 Microchip Technology Inc. PIC18F66K80 FAMILY 8.2 EECON1 and EECON2 Registers Access to the data EEPROM is controlled by two registers: EECON1 and EECON2 ...

  • Page 146

    ... When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error Note 1: condition. DS39977C-page 146 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/S-0 R/S bit Bit is unknown  2011 Microchip Technology Inc. ...

  • Page 147

    ... The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY After a write sequence has been initiated, EECON1, EEADRH:EEADR and EEDATA cannot be modified. ...

  • Page 148

    ... Data Memory Value to write ; Point to DATA memory ; Access EEPROM ; Enable writes ; Disable Interrupts ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete GOTO $-2 ; Enable Interrupts ; User code execution ; Disable writes on write complete (EEIF set) Preliminary  2011 Microchip Technology Inc. ...

  • Page 149

    ... LOOP INCFSZ EEADRH, F BRA LOOP BCF EECON1, WREN BSF INTCON, GIE  2011 Microchip Technology Inc. PIC18F66K80 FAMILY 8.8 Using the Data EEPROM The data EEPROM is a high-endurance, byte- and write addressable array that has been optimized for the storage of frequently changing information (e.g., pro- gram variables or other data that are updated often) ...

  • Page 150

    ... Bit 5 Bit 4 Bit 3 TMR0IE INT0IE RBIE TMR0IF — FREE WRERR CMP2IP CMP1IP — CCP5IP CMP2IF CMP1IF — CCP5IF CMP2IE CMP1IE — CCP5IE Preliminary Bit 2 Bit 1 Bit 0 INT0IF RBIF WREN WR RD CCP4IP CCP3IP CCP4IF CCP3IF CCP4IE CCP3IE  2011 Microchip Technology Inc. ...

  • Page 151

    ... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply  2011 Microchip Technology Inc. PIC18F66K80 FAMILY EXAMPLE 9-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 9-2: MOVF ARG1, W MULWF ARG2 BTFSC ...

  • Page 152

    ... RES2 WREG ; RES3 ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products RES2 WREG ; RES3 ARG2H ARG2H:ARG2L neg? ; no, check ARG1 ARG1L RES2 ; ARG1H RES3 ; ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H RES3  2011 Microchip Technology Inc. ...

  • Page 153

    ... Individual interrupts can be disabled through their corresponding enable bits.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...

  • Page 154

    ... PEIE/GIEL IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Preliminary  2011 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...

  • Page 155

    ... PORTB and wait one additional instruction cycle. Each pin on PORTB for interrupt-on-change is individually enabled and disabled in the IOCB register default, all pins are enabled.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Interrupt flag bits are set when an interrupt Note: ...

  • Page 156

    ... This feature allows for software polling. DS39977C-page 156 R/W-1 R/W-x R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-x R/W-1 INT3IP RBIP bit Bit is unknown  2011 Microchip Technology Inc. ...

  • Page 157

    ... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding Note: enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY R/W-0 R/W-0 ...

  • Page 158

    ... R-0 R/W-0 R/W-0 TX1IF SSPIF TMR1GIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown  2011 Microchip Technology Inc. ...

  • Page 159

    ... TMR3 register overflowed (bit must be cleared in software TMR3 register did not overflow bit 0 TMR3GIF: TMR3 Gate Interrupt Flag bit 1 = Timer gate interrupt occurred (bit must be cleared in software timer gate interrupt occurred  2011 Microchip Technology Inc. PIC18F66K80 FAMILY U-0 R/W-0 R/W-0 — ...

  • Page 160

    ... No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 0 Unimplemented: Read as ‘ 0 ’ DS39977C-page 160 R-0 R/W-0 R/W-0 TX2IF CTMUIF CCP2IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 U-0 CCP1IF — bit Bit is unknown  2011 Microchip Technology Inc. ...

  • Page 161

    ... A TMR register capture occurred (bit must be cleared in software TMR register capture occurred Compare Mode TMR register compare match occurred (must be cleared in software TMR register compare match occurred PWM Mode Not used in PWM mode.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY R/W-0 U-0 R/W-0 CMP1IF — ...

  • Page 162

    ... FIFO has not reached full status as defined by the FIFO_HF bit DS39977C-page 162 R/W-0 R/W-0 R/W-0 TXB2IF TXB1IF TXB0IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RXB1IF RXB0IF/ FIFOFIF bit Bit is unknown  2011 Microchip Technology Inc. ...

  • Page 163

    ... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt  2011 Microchip Technology Inc. PIC18F66K80 FAMILY R/W-0 R/W-0 R/W-0 TX1IE SSPIE TMR1GIE U = Unimplemented bit, read as ‘ ...

  • Page 164

    ... Enabled 0 = Disabled bit 0 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled DS39977C-page 164 U-0 R/W-0 R/W-0 — BCLIE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2011 Microchip Technology Inc. R/W-0 R/W-0 TMR3IE TMR3GIE bit Bit is unknown ...

  • Page 165

    ... CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 CCP1IE: ECCP1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 Unimplemented: Read as ‘ 0 ’  2011 Microchip Technology Inc. PIC18F66K80 FAMILY R-0 R/W-0 R/W-0 TX2IE CTMUIE CCP2IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...

  • Page 166

    ... Interrupt disabled bit 0 CCP3IE: CCP3 Interrupt Flag bits 1 = Interrupt enabled 0 = Interrupt disabled DS39977C-page 166 R/W-0 U-0 R/W-0 CMP1IE — CCP5IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CCP4IE CCP3IE bit Bit is unknown  2011 Microchip Technology Inc. ...

  • Page 167

    ... RXB0IE: Receive Buffer 0 Interrupt Flag bit 1 = Interrupt enabled 0 = Interrupt disabled Mode 1: Unimplemented: Read as ‘ 0 ’ Mode 2: FIFOFIE: FIFO Full Interrupt Flag bit 1 = Interrupt enabled 0 = Interrupt disabled  2011 Microchip Technology Inc. PIC18F66K80 FAMILY R/W-0 R/W-0 R/W-0 TXB2IE TXB1IE TXB0IE U = Unimplemented bit, read as ‘0’ ...

  • Page 168

    ... TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39977C-page 168 R/W-1 R/W-1 R/W-1 TX1IP SSPIP TMR1GIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown  2011 Microchip Technology Inc. ...

  • Page 169

    ... Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR3GIP: TMR3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority  2011 Microchip Technology Inc. PIC18F66K80 FAMILY U-0 R/W-1 R/W-1 — BCLIP HLVDIP U = Unimplemented bit, read as ‘0’ ...

  • Page 170

    ... CCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 Unimplemented: Read as ‘ 0 ’ DS39977C-page 170 R/W-1 R/W-1 R/W-1 TX2IP CTMUIP CCP2IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 U-0 CCP1IP — bit Bit is unknown  2011 Microchip Technology Inc. ...

  • Page 171

    ... Low priority bit 1 CCP4IP: CCP4 Interrupt Priority bit 1 = High priority 0 = Low priority bit CCP3IP: CCP3 Interrupt Priority bits 1 = High priority 0 = Low priority  2011 Microchip Technology Inc. PIC18F66K80 FAMILY R/W-1 U-0 R/W-1 CMP1IP — CCP5IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...

  • Page 172

    ... FIFOFIE: FIFO Full Interrupt Flag bit 1 = High priority 0 = Low priority DS39977C-page 172 R/W-1 R/W-1 R/W-1 TXB2IP TXB1IP TXB0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 RXB1IP RXB0IP/ FIFOFIE bit Bit is unknown  2011 Microchip Technology Inc. ...

  • Page 173

    ... PD: Power-Down Detection Flag bit For details of bit operation, see bit 1 POR: Power-on Reset Status bit For details of bit operation, see bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see  2011 Microchip Technology Inc. PIC18F66K80 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘0’ ...

  • Page 174

    ... INT2IP priority bit, RBIP (INTCON2<0>). R/W-0 U-0 (1) (1) IOCB4 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary Section 13.0 “Timer0 U-0 U-0 U-0 — — — bit Bit is unknown  2011 Microchip Technology Inc. ...

  • Page 175

    ... RCON IPEN SBOREN Legend: Shaded cells are not used by the interrupts.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY If a fast return from interrupt is not used (see Section 6.3 “Data Memory Organization” may need to save the WREG, STATUS and BSR regis- ters on entry to the Interrupt Service Routine (ISR). Depending on the user’ ...

  • Page 176

    ... PIC18F66K80 FAMILY NOTES: DS39977C-page 176 Preliminary  2011 Microchip Technology Inc. ...

  • Page 177

    ... PORT I/O pins have diode protection to V Note 1:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY 11.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V All of the digital ports are 5 ...

  • Page 178

    ... Bit is cleared (1) (1) (2) (2) R/W-1 R/W-1 R/W-1 WPUB4 WPUB3 WPUB2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 R/W-0 — — CTMUDS bit Bit is unknown R/W-1 R/W-1 WPUB1 WPUB0 bit Bit is unknown  2011 Microchip Technology Inc. ...

  • Page 179

    ... U2OD: UART2 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled bit 0 U1OD: UART1 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled  2011 Microchip Technology Inc. PIC18F66K80 FAMILY FIGURE 11-2: 3.3V PIC18F66K80 V DD (at logic ‘1’) ...

  • Page 180

    ... EMI. The reduced transition time is the default slew rate for all ports. Section 23.0 R/W-0 R/W-0 (1) (2) (2) SLRE SLRD SLRC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (2) (2) (2) Preliminary R/W-0 R/W-0 R/W-0 (2) SLRB SLRA bit Bit is unknown  2011 Microchip Technology Inc. ...

  • Page 181

    ... RA5 and RA<3:0> are configured as Note: analog inputs on any Reset and are read as ‘ 0 ’.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY OSC2/CLKO/RA6 and serve as the external circuit connections for the exter- nal (primary) oscillator circuit (HS Oscillator modes) or the external clock input and output (EC Oscillator modes) ...

  • Page 182

    ... DIG LATA<7> data output; disabled when FOSC2 Configuration bit is set PORTA<7> data input; disabled when FOSC2 Configuration bit is set. I ANA Main oscillator input connection (HS, XT, and LP modes). I ANA Main external clock source input (EC modes). Preliminary Description  2011 Microchip Technology Inc. ...

  • Page 183

    ... Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used by PORTA. These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, Note 1: they are disabled and read as ‘ x ’.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY Bit 5 Bit 4 ...

  • Page 184

    ... The RB<3:2> pins are multiplexed as CTMU edge inputs. RB5 has an additional function for Timer3 and Timer1. It can be configured for Timer3 clock input or Timer1 external clock gate input. Preliminary  2011 Microchip Technology Inc. wake the device from delay. ...

  • Page 185

    ... Default pin assignment for T0CKI when the T0CKMX Configuration bit is set. 3: Default pin assignment for T3CKI for 28, 40 and 44-pin devices. Alternate pin assignment for T3CKI for 64-pin devices 4: when T3CKMX is cleared.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY I/O I/O Type O DIG LATB< ...

  • Page 186

    ... INT1IE CCP4OD CCP3OD CCP2OD ANSEL13 ANSEL12 ANSEL11 Preliminary Description Bit 2 Bit 1 Bit 0 RB2 RB1 RB0 LATB2 LATB1 LATB0 TRISB2 TRISB1 TRISB0 TMR0IF INT0IF RBIF TMR0IP INT3IP RBIP INT3IF INT2IF INT1IF CCP1OD U2OD U1OD ANSEL10 ANSEL9 ANSEL8  2011 Microchip Technology Inc. ...

  • Page 187

    ... CCP2OD (ODCON<3>).  2011 Microchip Technology Inc. PIC18F66K80 FAMILY When enabling peripheral functions, use care in defin- ing TRIS bits for each PORTC pin. Some peripherals can override the TRIS bit to make a pin an output or input. Consult the corresponding peripheral section for the correct TRIS bit settings ...

  • Page 188

    ... DIG Synchronous serial clock output (EUSART module); user must configure as an input. ST Synchronous serial clock input (EUSART module); user must configure as an input. DIG CCP3 compare/PWM output. Takes priority over port data. ST CCP3 capture input. Preliminary  2011 Microchip Technology Inc. ...

  • Page 189

    ... RC7 RC6 LATC LATC7 LATBC6 TRISC TRISC7 TRISC6 ODCON SSPOD CCP5OD Legend: Shaded cells are not used by PORTC.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY I/O Description Type DIG LATC<7> data output. ST PORTC<7> data input. ST CAN bus RX. ST Asynchronous serial receive data input (EUSART module). ...

  • Page 190

    ... EXAMPLE 11-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs Preliminary  2011 Microchip Technology Inc. . ...

  • Page 191

    ... O = Output Input, ANA = Analog Signal, DIG = CMOS Output Schmitt Trigger Buffer Input, Legend Don’t care (TRIS bit does not affect port direction or is overridden for this option) Pin assignment for 40 and 44-pin devices (PIC18F4XK80). Note 1:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY I/O I/O Type O DIG LATD< ...

  • Page 192

    ... TRISD5 TRISD4 TRISD3 (2) (2) RFPU RGPU — CCP4OD CCP3OD CCP2OD ANSEL13 ANSEL12 ANSEL11 Preliminary Description Bit 2 Bit 1 Bit 0 RD2 RD1 RD0 LATD2 LATD1 LATD0 TRISD2 TRISD1 TRISD0 — — CTMUDS CCP1OD U2OD U1OD ANSEL10 ANSEL9 ANSEL8  2011 Microchip Technology Inc. ...

  • Page 193

    ... Note 1: Alternate pin assignment for CANRX and CANTX on 64-pin devices (PIC18F6XK80) when the CANMX Configuration 2: bit is cleared.  2011 Microchip Technology Inc. PIC18F66K80 FAMILY weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on any device Reset. ...

  • Page 194

    ... RE5 RE4 RE3 LATE5 LATE4 — TRISE5 TRISE4 — (1) (1) RFPU RGPU — ANSEL5 ANSEL4 ANSEL3 Preliminary Description Bit 2 Bit 1 Bit 0 RE2 RE1 RE0 LATE2 LATE1 LATE0 TRISE2 TRISE1 TRISE0 — — CTMUDS ANSEL2 ANSEL1 ANSEL0  2011 Microchip Technology Inc. ...

  • Page 195

    ... RDPU REPU Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used by PORTF. Unimplemented on 28-pin devices; read as ‘ 0 ’. Note 1:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY On device Resets, pins, RF<7:1>, are Note: configured as analog inputs and are read as ‘ 0 ’. ...

  • Page 196

    ... Synchronous serial clock input (EUSART module); user must configure as an input. Preliminary INITIALIZING PORTG ; Initialize PORTG by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RG1:RG0 as ; outputs ; RG2 as input ; RG4:RG3 as inputs Description  2011 Microchip Technology Inc. ...

  • Page 197

    ... TRISG — — PADCFG1 RDPU REPU Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used by PORTG. Unimplemented on 28-pin devices. Read as ‘ 0 ’. Note 1:  2011 Microchip Technology Inc. PIC18F66K80 FAMILY I/O I/O Type O DIG LATG<4> data output PORTG<4> data input. ...

  • Page 198

    ... Set Interrupt Flag PSPIF (PIR1<7>) Note: The I/O pin has protection diodes to V Figure 11-5, Preliminary PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT RDx Pin CK Data Latch TRIS Latch Read RD ST Chip Select CS ST Write WR ST and  2011 Microchip Technology Inc. ...

  • Page 199

    ... General Purpose I/O mode bit 3-0 Unimplemented: Read as ‘ 0 ’ FIGURE 11-4: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF  2011 Microchip Technology Inc. PIC18F66K80 FAMILY R/W-0 U-0 PSPMODE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary ...

  • Page 200

    ... RD2 RD1 RD0 LATD2 LATD1 LATD0 TRISD2 TRISD1 TRISD0 RE2 RE1 RE0 LATE2 LATE1 LATE0 TRISE2 TRISE1 TRISE0 — — — TMR0IF INT0IF RBIF TMR1GIF TMR2IF TMR1IF TMR1GIE TMR2IE TMR1IE TMR1GIP TMR2IP TMR1IP TMR2MD TMR1MD TMR0MD  2011 Microchip Technology Inc. ...