PIC18F26K80-I/SO Microchip Technology, PIC18F26K80-I/SO Datasheet - Page 143

no-image

PIC18F26K80-I/SO

Manufacturer Part Number
PIC18F26K80-I/SO
Description
MCU PIC 64KB FLASH 28SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet

Specifications of PIC18F26K80-I/SO

Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (0.300", 7.50mm Width)
Controller Family/series
PIC18
Ram Memory Size
4KB
Cpu Speed
16MIPS
No. Of Pwm Channels
5
Embedded Interface Type
I2C, SPI, USART
Processor Series
PIC18F26K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F26K80-I/SO
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC18F26K80-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC18F26K80-I/SO
0
EXAMPLE 7-3:
7.5.2
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
7.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
TABLE 7-2:
 2011 Microchip Technology Inc.
TBLPTRU
TBPLTRH
TBLPTRL
TABLAT
INTCON
EECON2
EECON1
IPR4
PIR4
PIE4
Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used during Flash/EEPROM access.
Note 1:
PROGRAM_MEMORY
Name
Required
Sequence
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
EEPROM Control Register 2 (not a physical register)
GIE/GIEH
TMR4IP
TMR4IF
TMR4IE
EEPGD
Bit 7
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PEIE/GIEL TMR0IE
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
CFGS
EEIP
EEIE
Bit 6
EEIF
CMP2IP
CMP2IF
CMP2IE
bit 21
Bit 5
(1)
Preliminary
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
; write 55h
; write 0AAh
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
CMP1IP
CMP1IE
CMP1IF
INT0IE
FREE
Bit 4
PIC18F66K80 FAMILY
7.5.4
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See
CPU”
7.6
See
Protection”
program memory.
WRERR
RBIE
Bit 3
Section 28.6 “Program Verification and Code
for more detail.
Flash Program Operation During
Code Protection
PROTECTION AGAINST
SPURIOUS WRITES
for details on code protection of Flash
Section 28.0 “Special Features of the
TMR0IF
CCP5IP
CCP5IF
CCP5IE
WREN
Bit 2
CCP4IP
CCP4IF
CCP4IE
INT0IF
Bit 1
WR
DS39977C-page 143
CCP3IP
CCP3IF
CCP3IE
Bit 0
RBIF
RD

Related parts for PIC18F26K80-I/SO