PIC18F26K80-I/SO Microchip Technology, PIC18F26K80-I/SO Datasheet - Page 175

• Manufacturer Part Number: PIC18F26K80-I/SO
• Description: MCU PIC 64KB FLASH 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K80-I/SO

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F26K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.9
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack.
EXAMPLE 10-1:
TABLE 10-1:
 2011 Microchip Technology Inc.
INTCON
INTCON2
INTCON3
PIR1
PIR2
PIR3
PIR4
PIR5
PIE1
PIE2
PIE3
PIE4
PIE5
IPR1
IPR2
IPR3
IPR4
IPR5
RCON
Legend: Shaded cells are not used by the interrupts.
MOVWF
MOVFF
MOVFF
;
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
Name
Context Saving During Interrupts
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
GIE/GIEH
OSCFIE
OSCFIP
OSCFIF
TMR4IF
TMR4IE
TMR4IP
INT2IP
PSPIP
PSPIE
PSPIP
RBPU
IRXIF
IRXIE
IRXIP
IPEN
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Bit 7
—
—
—
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
PEIE/GIEL
INTEDG0
SBOREN
WAKIE
WAKIP
INT1IP
WAKIF
ADIE
ADIP
ADIF
EEIF
EEIE
EEIP
Bit 6
—
—
—
—
—
—
INTEDG1
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
TMR0IE
CMP2IF
CCP2IE
CMP2IP
INT3IE
ERRIF
RC1IE
RC2IE
ERRIE
RC1IP
RC2IP
ERRIP
RC1IF
RC2IF
Bit 5
CM
—
—
—
Preliminary
INTEDG2
CMP1IF
CMP1IE
CMP1IP
TXB2IE
TXB2IP
TXB2IF
INT0IE
INT2IE
TX1IF
TX2IF
TX1IE
TX2IE
TX1IP
TX2IP
Bit 4
—
—
—
RI
PIC18F66K80 FAMILY
If a fast return from interrupt is not used (see
Section 6.3 “Data Memory Organization”
may need to save the WREG, STATUS and BSR regis-
ters on entry to the Interrupt Service Routine (ISR).
Depending on the user’s application, other registers
also may need to be saved.
Example 10-1
and BSR registers during an Interrupt Service Routine.
INTEDG3
CTMUIF
CTMUIE
CTMUIP
TXB1IF
TXB1IE
TXB1IP
INT1IE
SSPIE
SSPIP
SSPIF
BCLIF
BCLIE
BCLIP
RBIE
Bit 3
TO
—
—
—
saves and restores the WREG, STATUS
TMR1GIF
TMR1GIE
TMR1GIP
TMR0IP
TMR0IF
CCP2IF
CCP5IF
HLVDIE
CCP2IE
CCP5IE
HLVDIP
CCP2IP
CCP5IP
HLVDIF
TXB0IF
TXB0IE
TXB0IP
INT3IF
Bit 2
PD
TMR2IF
TMR3IF
TMR2IE
TMR3IE
CCP1IE
CCP4IE
TMR2IP
TMR3IP
CCP1IP
CCP4IP
CCP1IF
CCP4IF
RXB1IF
RXB1IE
RXB1IP
INT0IF
INT3IP
INT2IF
Bit 1
POR
DS39977C-page 175
TMR3GIE
TMR3GIP
TMR3GIF
TMR1IE
TMR1IP
), the user
TMR1IF
CCP3IF
RXB0IF
CCP3IE
RXB0IE
CCP3IP
RXB0IP
INT1IF
RBIP
Bit 0
RBIF
BOR
—
—
—