PIC18F26K80-I/SO Microchip Technology, PIC18F26K80-I/SO Datasheet - Page 185

• Manufacturer Part Number: PIC18F26K80-I/SO
• Description: MCU PIC 64KB FLASH 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K80-I/SO

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F26K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 11-3:
 2011 Microchip Technology Inc.
RB0/AN10/C1INA
FLT0/INT0
RB1/AN8/C1INB/
P1B/CTDIN/INT1
RB2/CANTX/C1OUT/
P1C/CTED1/INT2
RB3/CANRX/
C2OUT/P1D/
CTED2/INT3
RB4/AN9/C2INA/
ECCP1/P1A/CTPLS/
KBI0
Legend:
Note 1:
Pin Name
2:
3:
4:
O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Pin assignment only available for 28-pin devices (PIC18F2XK80).
Default pin assignment for CANRX and CANTX when the CANMX Configuration bit is set.
Default pin assignment for T0CKI when the T0CKMX Configuration bit is set.
Default pin assignment for T3CKI for 28, 40 and 44-pin devices. Alternate pin assignment for T3CKI for 64-pin devices
when T3CKMX is cleared.
PORTB FUNCTIONS
CANTX
C1OUT
CANRX
C2OUT
Function
ECCP1
C1INA
C1INB
C2INA
CTED1
CTED2
CTPLS
CTDIN
P1B
P1C
P1D
P1A
AN10
FLT0
INT0
INT1
INT2
INT3
KBI0
RB0
RB1
AN8
RB2
RB3
RB4
AN9
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(1)
(1)
(1)
(2)
Setting
TRIS
0
1
1
1
x
1
0
1
1
1
0
1
1
0
1
0
0
0
x
1
0
1
1
x
0
x
1
0
1
1
2
0
1
0
x
1
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O Type
Preliminary
ANA
ANA
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
LATB<0> data output.
PORTB<0> data input; weak pull-up when RBPU bit is cleared.
A/D Input Channel 10 and Comparator C1+ input. Default input
configuration on POR.
Comparator 1 Input A.
Enhanced PWM Fault input for ECCPx.
External Interrupt 0 input.
LATB<1> data output.
PORTB<1> data input; weak pull-up when RBPU bit is cleared.
A/D Input Channel 8 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
Comparator 1 Input B.
ECCP1 PWM Output B. May be configured for tri-state during
Enhanced PWM shutdown events.
CTMU pulse delay input.
External Interrupt 1 input.
LATB<2> data output.
PORTB<2> data input; weak pull-up when RBPU bit is cleared.
CAN bus TX.
Comparator 1 output; takes priority over port data.
ECCP1 PWM Output C. May be configured for tri-state during
Enhanced PWM.
CTMU Edge 1 input.
External Interrupt 2.
LATB<3> data output.
PORTB<3> data input; weak pull-up when RBPU bit is cleared.
CAN bus RX.
CTMU Edge 2 input.
ECCP1 PWM Output D. May be configured for tri-state during
Enhanced PWM.
CTMU Edge 2 input.
External Interrupt 3 input.
LATB<4> data output.
PORTB<4> data input; weak pull-up when RBPU bit is cleared.
A/D Input Channel 9 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
Comparator 2 Input A.
ECCP1 compare output and ECCP1 PWM output. Takes priority
over port data.
ECCP1 capture input.
ECCP1 Enhanced PWM output, Channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority
over port data.
CTMU pulse generator output.
Interrupt-on-pin change.
PIC18F66K80 FAMILY
Description
DS39977C-page 185