PIC18F26K80-I/SO Microchip Technology, PIC18F26K80-I/SO Datasheet - Page 305

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PIC18F26K80-I/SO

Manufacturer Part Number
PIC18F26K80-I/SO
Description
MCU PIC 64KB FLASH 28SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet

Specifications of PIC18F26K80-I/SO

Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (0.300", 7.50mm Width)
Controller Family/series
PIC18
Ram Memory Size
4KB
Cpu Speed
16MIPS
No. Of Pwm Channels
5
Embedded Interface Type
I2C, SPI, USART
Processor Series
PIC18F26K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F26K80-I/SO
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC18F26K80-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC18F26K80-I/SO
0
REGISTER 21-5:
 2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
GCEN
R/W-0
2:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
If the I
writes to the SSPBUF are disabled).
GCEN: General Call Enable bit
Unused in Master mode.
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit
1 = Initiates Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically
0 = Acknowledge sequence Idle
RCEN: Receive Enable bit (Master Receive mode only)
1 = Enables Receive mode for I
0 = Receive Idle
PEN: Stop Condition Enable bit
1 = Initiates Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
RSEN: Repeated Start Condition Enable bit
1 = Initiates Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
SEN: Start Condition Enable bit
1 = Initiates Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
ACKSTAT
2
R/W-0
C module is active, these bits may not be set (no spooling) and the SSPBUF may not be written (or
cleared by hardware.
SSPCON2: MSSP CONTROL REGISTER 2 (I
W = Writable bit
‘1’ = Bit is set
ACKDT
R/W-0
(1)
ACKEN
(2)
(2)
2
C™
R/W-0
Preliminary
(2)
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
PIC18F66K80 FAMILY
RCEN
R/W-0
(2)
(2)
2
(1)
C™ MASTER MODE)
PEN
R/W-0
(2)
x = Bit is unknown
RSEN
R/W-0
(2)
DS39977C-page 305
SEN
R/W-0
(2)
bit 0

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