PIC18F26K80-I/SO Microchip Technology, PIC18F26K80-I/SO Datasheet - Page 369

• Manufacturer Part Number: PIC18F26K80-I/SO
• Description: MCU PIC 64KB FLASH 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K80-I/SO

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F26K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The ANCONx registers are used to configure the
operation of the I/O pin associated with each analog
channel. Clearing an ANSELx bit configures the
corresponding pin (ANx) to operate as a digital only I/O.
Setting a bit configures the pin to operate as an analog
input for either the A/D Converter or the comparator
REGISTER 23-8:
REGISTER 23-9:
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(AV
RA3/V
two additional internal voltage reference selections:
2.048V and 4.096V.
The A/D Converter can uniquely operate while the
device is in Sleep mode. To operate in Sleep , the A/D
conversion clock must be derived from the A/D’s
internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
 2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-0
Note 1:
ANSEL7
DD
R/W-x
U-1
—
REF
and AV
+/AN3 and RA2/V
(1)
AN14 through AN11 and AN7 to AN5 are implemented only on 40/44-pin and 64-pin devices. For 28-pin
devices, the corresponding ANSELx bits are still implemented for these channels, but have no effect.
AN14 through AN11 and AN7 to AN5 are implemented only on 40/44-pin and 64-pin devices. For 28-pin
devices, the corresponding ANSELx bits are still implemented for these channels, but have no effect.
ANSEL<7:0>: Analog Port Configuration bits (AN7 and AN0)
1 = Pin configured as an analog channel: digital input disabled and any inputs read as ‘ 0 ’
0 = Pin configured as a digital port
Unimplemented: Read as ‘ 0 ’
ANSEL<14:8>: Analog Port Configuration bits (AN14 through AN8)
1 = Pin configured as an analog channel: digital input disabled and any inputs read as ‘ 0 ’
0 = Pin configured as a digital port
ANSEL14
ANSEL6
SS
R/W-x
R/W-x
) or the voltage level on the
ANCON0: A/D PORT CONFIGURATION REGISTER 0
ANCON1: A/D PORT CONFIGURATION REGISTER 1
(1)
(1)
REF
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
ANSEL13
ANSEL5
-/AN2 pins. V
R/W-x
R/W-x
(1)
(1)
REF
ANSEL12
ANSEL4
R/W-x
R/W-x
+ has
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ANSEL11
PIC18F66K80 FAMILY
ANSEL3
R/W-x
R/W-x
module, with all digital peripherals disabled and digital
inputs read as ‘ 0 ’.
As a rule, I/O pins that are multiplexed with analog
inputs default to analog operation on any device Reset.
Each port pin associated with the A/D Converter can be
configured as an analog input or a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0<1>) is cleared
and the A/D Interrupt Flag bit, ADIF (PIR1<6>), is set.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted. The value in the
ADRESH:ADRESL register pair is not modified for a
Power-on Reset. These registers will contain unknown
data after a Power-on Reset.
The block diagram of the A/D module is shown in
Figure
(1)
23-4.
ANSEL10
(1)
ANSEL2
R/W-x
R/W-x
(1)
x = Bit is unknown
x = Bit is unknown
ANSEL1
ANSEL9
R/W-x
R/W-x
DS39977C-page 369
ANSEL0
ANSEL8
R/W-x
R/W-x
bit 0
bit 0