PIC18F26K80-I/SO Microchip Technology, PIC18F26K80-I/SO Datasheet - Page 383

• Manufacturer Part Number: PIC18F26K80-I/SO
• Description: MCU PIC 64KB FLASH 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K80-I/SO

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F26K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.6
The comparator interrupt flag is set whenever any of
the following occurs:
• Low-to-high transition of the comparator output
• High-to-low transition of the comparator output
• Any change in the comparator output
The comparator interrupt selection is done by the
EVPOL<1:0>
(CMxCON<4:3>).
In order to provide maximum flexibility, the output of the
comparator may be inverted using the CPOL bit in the
CMxCON register (CMxCON<5>). This is functionally
identical to reversing the inverting and non-inverting
inputs of the comparator for a particular mode.
An interrupt is generated on the low-to-high or high-to-
low transition of the comparator output. This mode of
interrupt generation is dependent on EVPOL<1:0> in
the CMxCON register. When EVPOL<1:0> = 01 or 10 ,
the interrupt is generated on a low-to-high or high-to-
low transition of the comparator output. Once the
interrupt is generated, it is required to clear the interrupt
flag by software.
TABLE 24-2:
 2011 Microchip Technology Inc.
CPOL
Comparator Interrupts
0
1
bits
COMPARATOR INTERRUPT GENERATION
in
EVPOL<1:0>
the
00
01
10
11
00
01
10
11
CMxCON
register
Input Change
Comparator
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Preliminary
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
+ > V
+ < V
+ > V
+ < V
+ > V
+ < V
+ > V
+ < V
+ > V
+ < V
+ > V
+ < V
+ > V
+ < V
+ > V
+ < V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PIC18F66K80 FAMILY
When EVPOL<1:0> = 11 , the comparator interrupt flag
is set whenever there is a change in the output value of
either comparator. Software will need to maintain
information about the status of the output bits, as read
from CMSTAT<7:6>, to determine the actual change
that occurred.
The CMPxIF<2:0> (PIR4<5:4) bits are the Comparator
Interrupt Flags. The CMPxIF bits must be reset by
clearing them. Since it is also possible to write a ‘ 1 ’ to
this register, a simulated interrupt may be initiated.
Table 24-2
to comparator input voltages and EVPOL bit settings.
Both the CMPxIE bits (PIE4<5:4>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit (INTCON<7>) must also be set. If
any of these bits are clear, the interrupt is not enabled,
though the CMPxIF bits will still be set if an interrupt
condition occurs.
A simplified diagram of the interrupt section is shown in
Figure
Note:
24-3.
CxOUT Transition
Low-to-High
High-to-Low
Low-to-High
High-to-Low
Low-to-High
High-to-Low
Low-to-High
High-to-Low
High-to-Low
Low-to-High
High-to-Low
Low-to-High
High-to-Low
Low-to-High
High-to-Low
Low-to-High
shows the interrupt generation with respect
CMPxIF
EVPOL<1:0> = 00 .
will
not
DS39977C-page 383
be
Generated
Interrupt
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
set
when