PIC18F26K80-I/SO Microchip Technology, PIC18F26K80-I/SO Datasheet - Page 63

• Manufacturer Part Number: PIC18F26K80-I/SO
• Description: MCU PIC 64KB FLASH 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K80-I/SO

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F26K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.6.3
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 16 MHz. It
can be adjusted in the user’s application by writing to
TUN<5:0>
register
When the OSCTUNE register is modified, the INTOSC
(HF-INTOSC and MF-INTOSC) frequency will begin
shifting to the new frequency. The oscillator will require
some time to stabilize. Code execution continues
during this shift and there is no indication that the shift
has occurred.
The LF-INTOSC oscillator operates independently of
the HF-INTOSC or the MF-INTOSC source. Any
changes in the HF-INTOSC or the MF-INTOSC source,
across voltage and temperature, are not necessarily
reflected by changes in LF-INTOSC or vice versa. The
frequency of LF-INTOSC is not affected by OSCTUNE.
3.6.4
The INTOSC frequency may drift as V
ture changes and can affect the controller operation in
a variety of ways. It is possible to adjust the INTOSC
frequency by modifying the value in the OSCTUNE
register. Depending on the device, this may have no
effect on the LF-INTOSC clock source frequency.
Tuning INTOSC requires knowing when to make the
adjustment, in which direction it should be made, and in
some cases, how large a change is needed. Three
compensation techniques are shown here.
3.6.4.1
An adjustment may be required when the EUSART
begins to generate framing errors or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high. To
adjust for this, decrement the value in OSCTUNE to
reduce the clock frequency. On the other hand, errors
in data may suggest that the clock speed is too low. To
compensate, increment OSCTUNE to increase the
clock frequency.
3.6.4.2
This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the SOSC
oscillator.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is much greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.
 2011 Microchip Technology Inc.
(Register
INTERNAL OSCILLATOR OUTPUT
FREQUENCY AND TUNING
INTOSC FREQUENCY DRIFT
(OSCTUNE<5:0>)
Compensating with the EUSART
Compensating with the Timers
3-3).
in
the
DD
or tempera-
OSCTUNE
Preliminary
PIC18F66K80 FAMILY
3.6.4.3
A CCP module can use free-running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast. To compensate, decrement the OSCTUNE
register. If the measured time is much less than the
calculated time, the internal oscillator block is running
too slow. To compensate, increment the OSCTUNE
register.
3.7
In addition to the F
oscillator modes, the device clock in the PIC18F66K80
family can also be configured to provide a reference
clock output signal to a port pin. This feature is avail-
able in all oscillator configurations and allows the user
to select a greater range of clock submultiples to drive
external devices in the application.
This reference clock output is controlled by the
REFOCON register
bit (REFOCON<7>) makes the clock signal available
on the REFO (RC3) pin. The RODIV<3:0> bits enable
the selection of 16 different clock divider options.
The ROSSLP and ROSEL bits (REFOCON<5:4>) con-
trol the availability of the reference output during Sleep
mode. The ROSEL bit determines if the oscillator on
OSC1 and OSC2, or the current system clock source,
is used for the reference clock output. The ROSSLP bit
determines if the reference source is available on RE3
when the device is in Sleep mode.
To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
clock must also be configured for an EC or HS mode. If
not, the oscillator on OSC1 and OSC2 will be powered
down when the device enters Sleep mode. Clearing the
ROSEL bit allows the reference output frequency to
change as the system clock changes during any clock
switches.
Reference Clock Output
Compensating with the CCP Module
in Capture Mode
(Register
OSC
/4 clock output, in certain
3-4). Setting the ROON
DS39977C-page 63