LPC1768FET100,551 NXP Semiconductors, LPC1768FET100,551 Datasheet - Page 21

• Manufacturer Part Number: LPC1768FET100,551
• Description: IC MCU 32BIT 512KB FLASH 100LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1768FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC1768
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: Ethernet, USB, CAN, I2S, I2C
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-5215

NXP Semiconductors
LPC1769_68_67_66_65_64_63
Product data sheet
7.7.1 Features
7.7.2 Interrupt sources
7.7 Nested Vectored Interrupt Controller (NVIC)
7.8 Pin connect block
7.9 General purpose DMA controller
The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any pin on Port 0 and Port 2 (total of 42 pins) regardless of the selected function, can be
programmed to generate an interrupt on a rising edge, a falling edge, or both.
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or
no resistor enabled.
The GPDMA is an AMBA AHB compliant peripheral allowing selected peripherals to have
DMA support.
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. The source and
destination areas can each be either a memory region or a peripheral, and can be
accessed through the AHB master. The GPDMA controller allows data transfers between
the USB and Ethernet controllers and the various on-chip SRAM areas. The supported
APB peripherals are SSP0/1, all UARTs, the I
Two match signals for each timer can be used to trigger DMA transfers.
Remark: The Ethernet controller is available on parts LPC1769/68/67/66/64. The USB
controller is available on parts LPC1769/68/66/65/64. The I
parts LPC1769/68/67/66/65. The DAC is available on parts LPC1769/68/67/66/65/63.
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Controls system exceptions and peripheral interrupts
In the LPC17xx, the NVIC supports 33 vectored interrupts
32 programmable interrupt priority levels, with hardware priority level masking
Relocatable vector table
Non-Maskable Interrupt (NMI)
Software interrupt generation
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 5 April 2011
LPC1769/68/67/66/65/64/63
2
S-bus interface, the ADC, and the DAC.
32-bit ARM Cortex-M3 microcontroller
2
S-bus interface is available on
© NXP B.V. 2011. All rights reserved.
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