LPC1768FET100,551 NXP Semiconductors, LPC1768FET100,551 Datasheet - Page 38

IC MCU 32BIT 512KB FLASH 100LQFP

LPC1768FET100,551

Manufacturer Part Number
LPC1768FET100,551
Description
IC MCU 32BIT 512KB FLASH 100LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheet

Specifications of LPC1768FET100,551

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC1768
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
Ethernet, USB, CAN, I2S, I2C
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
568-5215

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC1768FET100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
LPC1769_68_67_66_65_64_63
Product data sheet
7.29.8 Power domains
The LPC17xx provide two independent power domains that allow the bulk of the device to
have power removed while maintaining operation of the RTC and the backup Registers.
On the LPC17xx, I/O pads are powered by the 3.3 V (V
V
CPU and most of the peripherals.
Depending on the LPC17xx application, a design can use two power options to manage
power consumption.
The first option assumes that power consumption is not a concern and the design ties the
V
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (V
a dedicated 3.3 V supply for the CPU (V
powered independently from the I/O pad ring enables shutting down of the I/O pad power
supply “on the fly”, while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of
power to operate, which can be supplied by an external battery. The device core power
(V
there is no power drain from the RTC battery when V
DD(REG)(3V3)
DD(3V3)
DD(REG)(3V3)
and V
pin powers the on-chip voltage regulator which in turn provides power to the
) is used to operate the RTC whenever V
DD(REG)(3V3)
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 5 April 2011
pins together. This approach requires only one 3.3 V power
LPC1769/68/67/66/65/64/63
DD(REG)(3V3)
32-bit ARM Cortex-M3 microcontroller
). Having the on-chip voltage regulator
DD(REG)(3V3)
DD(REG)(3V3)
DD(3V3)
) pins, while the
is available.
is present. Therefore,
© NXP B.V. 2011. All rights reserved.
DD(3V3)
38 of 79
) and

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