LPC1768FET100,551 NXP Semiconductors, LPC1768FET100,551 Datasheet - Page 39

• Manufacturer Part Number: LPC1768FET100,551
• Description: IC MCU 32BIT 512KB FLASH 100LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1768FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC1768
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: Ethernet, USB, CAN, I2S, I2C
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-5215

NXP Semiconductors
LPC1769_68_67_66_65_64_63
Product data sheet
7.30.1 Reset
7.30 System control
Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains
a usable level, causes the RSTOUT pin to go LOW and starts the wake-up timer (see
description in
until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks
have passed, and the flash controller has completed its initialization. Once reset is
de-asserted, or, in case of a BOD-triggered reset, once the voltage rises above the BOD
threshold, the RSTOUT pin goes HIGH.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Fig 6.
Power distribution
V
DD(REG)(3V3)
Section
All information provided in this document is subject to legal disclaimers.
V
DD(3V3)
VREFP
VREFN
RTCX1
RTCX2
VBAT
V
V
V
DDA
SSA
SS
7.29.5). The wake-up timer ensures that reset remains asserted
Rev. 7 — 5 April 2011
LPC17xx
LPC1769/68/67/66/65/64/63
RTC POWER DOMAIN
ADC POWER DOMAIN
MAIN POWER DOMAIN
OSCILLATOR
SELECTOR
to I/O pads
POWER
32 kHz
REGULATOR
32-bit ARM Cortex-M3 microcontroller
ULTRA LOW-POWER
REGULATOR
BACKUP REGISTERS
DAC
ADC
REAL-TIME CLOCK
to core
to memories,
peripherals,
oscillators,
PLLs
002aad978
© NXP B.V. 2011. All rights reserved.
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