LPC1768FET100,551 NXP Semiconductors, LPC1768FET100,551 Datasheet - Page 56

• Manufacturer Part Number: LPC1768FET100,551
• Description: IC MCU 32BIT 512KB FLASH 100LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1768FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC1768
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: Ethernet, USB, CAN, I2S, I2C
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-5215

NXP Semiconductors
Table 14.
T
[1]
LPC1769_68_67_66_65_64_63
Product data sheet
Symbol
common to input and output
t
t
t
t
output
t
input
t
t
r
f
WH
WL
v(Q)
su(D)
h(D)
amb
Fig 17. I
CCLK = 20 MHz; peripheral clock to the I
signal in the I
=
SDA
SCL
−
40
2
°
C-bus pins clock timing
Dynamic characteristics: I
Parameter
rise time
fall time
pulse width HIGH
pulse width LOW
data output valid time
data input set-up time
data input hold time
C to +85
70 %
30 %
S
2
11.6 I
S-bus specification.
t
f
°
C.
t
f
70 %
Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See
Table
30 %
2
S-bus interface
1 / f
2.
SCL
t
HD;DAT
70 %
30 %
2
Conditions
on pins I2STX_CLK and
I2SRX_CLK
on pins I2STX_CLK and
I2SRX_CLK
on pin I2STX_SDA
on pin I2STX_WS
on pin I2SRX_SDA
on pin I2SRX_SDA
2
S-bus interface pins
S-bus interface PCLK =
70 %
30 %
All information provided in this document is subject to legal disclaimers.
t
SU;DAT
Rev. 7 — 5 April 2011
70 %
30 %
LPC1769/68/67/66/65/64/63
CCLK
t
LOW
⁄
4
; I
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
2
S clock cycle time T
t
Min
-
-
0.495 × T
-
-
-
3.5
4.0
HIGH
32-bit ARM Cortex-M3 microcontroller
70 %
30 %
cy(clk)
t
VD;DAT
cy(clk)
Typ
-
-
-
-
-
-
-
-
= 1600 ns, corresponds to the SCK
Max
35
35
-
0.505 × T
30
30
-
-
© NXP B.V. 2011. All rights reserved.
002aaf425
cy(clk)
Unit
ns
ns
-
ns
ns
ns
ns
ns
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