STM32F101VGT6 STMicroelectronics, STM32F101VGT6 Datasheet - Page 60

MCU ARM 32BIT 1MB FLASH 100LQFP

STM32F101VGT6

Manufacturer Part Number
STM32F101VGT6
Description
MCU ARM 32BIT 1MB FLASH 100LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F101VGT6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
36MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Processor Series
STM32F101xG
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
80 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
112
Number Of Timers
15
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 105 C
Processor To Be Evaluated
STM32F101VG
Supply Current (max)
28 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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0
Electrical characteristics
60/108
Table 32.
1. C
2. Preliminary values.
Figure 23. Asynchronous multiplexed NOR/PSRAM read waveforms
Table 33.
t
t
t
t
t
t
t
t
t
t
t
v(NADV_NE)
w(NADV)
w(NE)
v(NOE_NE)
w(NOE)
h(NE_NOE)
v(A_NE)
v(NADV_NE)
w(NADV)
h(AD_NADV)
h(A_NOE)
Symbol
Symbol
L
= 15 pF.
FSMC_NBL[1:0]
FSMC_ AD[15:0]
FSMC_A[25:16]
FSMC_NADV
FSMC_NWE
FSMC_NOE
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Asynchronous multiplexed NOR/PSRAM read timings
FSMC_NE
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
FSMC_NE low time
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
FSMC_NOE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
FSMC_AD (address) valid hold time after
FSMC_NADV high
Address hold time after FSMC_NOE high
Parameter
Parameter
Doc ID 17143 Rev 2
t
t
t
v(NADV_NE)
v(A_NE)
v(A_NE)
t
t
t
v(NOE_NE)
v(BL_NE)
w(NADV)
Address
Address
t
h(AD_NADV)
t
w(NE)
NBL
t
su(Data_NOE)
t
t
w(NOE)
su(Data_NE)
7T
3T
4T
–1
3
T
T
T
Data
HCLK
HCLK
HCLK
STM32F101xF, STM32F101xG
HCLK
HCLK
HCLK
t
h(NE_NOE)
t
Min
Min
h(BL_NOE)
t
h(A_NOE)
–1.5
– 2
– 0.5 3T
– 1
(1)(2)
7T
4T
0
5
T
T
5.5
HCLK
HCLK
HCLK
HCLK
HCLK
Max
Max
t
h(Data_NOE)
t
+ 1.5
h(Data_NE)
+ 1.5
+ 2
+ 1.5
+ 2
ai14892b
(1)(2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Unit

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