MC56F8257VLH Freescale Semiconductor, MC56F8257VLH Datasheet

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... Any pin, except Power pins and the Reset pin, can also be configured as General Purpose Input/Outputs (GPIOs). Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2009-2011. All rights reserved. Document Number: MC56F825X MC56F825x/MC56F824x 44-pin LQFP ...

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... HSCMP Specifications . . . . . . . . . . . . . . . . . . . . . . . . 71 7.29 Optimize Power Consumption . . . . . . . . . . . . . . . . . . . 71 8 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.1 Thermal Design Considerations . . . . . . . . . . . . . . . . . 72 8.2 Electrical Design Considerations Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10 Package Mechanical Outline Drawings . . . . . . . . . . . . . . . . . 76 10.1 44-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.2 48-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.3 64-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Appendix A Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Freescale Semiconductor ...

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... Operating temperature range Package 1 Can be clocked by high speed peripheral clock up to 120 MHz 2 Can be clocked by high speed peripheral clock up to 120 MHz 3 Shared with other function pins MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor MC56F825x/MC56F824x Family Configuration 56F8245 56F8246 56F8247 56F8255 56F8256 56F8257 ...

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... Three user programmable priority levels for each interrupt source: Level — Unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, and SWI3 instruction — Maskable level 3 interrupts include: EOnCE step counter, EOnCE breakpoint unit, and EOnCE trace buffer MC56F825x/MC56F824x Digital Signal Controller, Rev Freescale Semiconductor ...

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... Crossbar module outputs – External ADC input, taking into account values set in ADC high and low limit registers • Two independent 12-bit analog-to-digital converters (ADCs) — channel external inputs — Built-in x1, x2, x4 programmable gain pre-amplifier MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor Overview 5 ...

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... Full-duplex operation — Four-word deep FIFOs available on both transmit and receive buffers — Master and slave modes — Programmable length transactions ( bits) — Programmable transmit and receive shift order (MSB as first or last bit transmitted) MC56F825x/MC56F824x Digital Signal Controller, Rev Freescale Semiconductor ...

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... Programmable initial seed value — High-speed hardware CRC calculation — Optional feature to transpose input data and CRC result via transpose register, required on applications where bytes are in LSb (Least Significant bit) format. MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor 2 C) ports Overview 7 ...

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... Architecture Block Diagram The MC56F825x/MC56F824x’s architecture appears in buses communicate with internal memories and the IP bus interface as well as the internal connections among the units of the 56800E core. MC56F825x/MC56F824x Digital Signal Controller, Rev Figure 1 and Figure 2. Figure 1 illustrates how the 56800E system Freescale Semiconductor ...

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... IP bus bridge. Refer to the system integration module (SIM) section in the device’s reference manual for information about which signals are multiplexed with those of other peripherals. MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor DSP56800E Core ALU1 ...

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... Overview MC56F825x/MC56F824x Digital Signal Controller, Rev Figure 2. Peripheral Subsystem Freescale Semiconductor ...

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... Product Documentation The documents listed in Table 2 are required for a complete description and proper design with the MC56F825x/MC56F824x. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com. Table 2. MC56F825x/MC56F824x Device Documentation Topic DSP56800E Reference Manual ...

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... Cross Bar COMP Power JTAG Misc. Timer PWM XB_IN2 TB0 TB1 CMPA_O TA0 CMPB_O TA1 CMPA_P2/ CMPC_O CMPA_M0 CMPA_M1 CMPA_M2 CMPB_M2 XB_IN7 CMPB_M1 CMPC_M2 CMPC_M1 V DDA V SSA CMPB_P2 CMPB_M0 V CAP CMPC_P2 Freescale Semiconductor TCK RESET XTAL/ CLKIN EXTAL CLKO DACO ...

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... GPIOE5/PWM2A/XB_IN3 53 GPIOE6/PWM3B/XB_IN4 54 GPIOE7/PWM3A/XB_IN5 GPIOC14/SDA0/XB_OUT0 GPIOC15/SCL0/XB_OUT1 CAP 58 GPIOF6/TB2/PWM3X 59 GPIOF7/TB3 MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor MS 2 GPIO I C SCI SPI ADC 1 CAN ANB3& GPIOB3 VREFLB GPIOC6 TXD0 SS GPIOC7 RXD0 MISO GPIOC8 SCLK GPIOC9 MOSI/ MISO GPIOF0 CANTX CANRX GPIOF2 SCL1 GPIOF3 SDA1 ...

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... TDI/GPIOD0 1 The MSCAN module is not available on the MC56F824x devices. MC56F825x/MC56F824x Digital Signal Controller, Rev GPIO I C SCI SPI ADC 1 CAN GPIOD1 GIPOD3 GPIOD0 Peripherals Quad eFlex Cross Bar COMP Power JTAG Misc. Timer PWM V SS Freescale Semiconductor TDO TMS TDI ...

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... The CANRX and CANTX signals of the MSCAN module are not available on the MC56F824x devices. GPIOD2/TCK GPIOD4/RESET GPIOC0/XTAL/CLKIN GPIOC1/EXTAL GPIOC2/TXD0/TB0/XB_IN2/CLKO GPIOC3/TA0/CMPA_O/RXD0 GPIOC4/TA1/CMPB_O GPIOA0/ANA0/CMPA_P2/CMPC_O GPIOA1/ANA1/CMPA_M0 GPIOA2/ANA2/VREFHA/CMPA_M1 GPIOA3/ANA3/VREFLA/CMPA_M2 Figure 3. Top View: 56F8245 and 56F8255 44-Pin LQFP Package MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor NOTE ...

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... GPIOA2/ANA2/VREFHA/CMPA_M1 GPIOA3/ANA3/VREFLA/CMPA_M2 Figure 4. Top View: 56F8246 and 56F8256 48-Pin LQFP Package MC56F825x/MC56F824x Digital Signal Controller, Rev GPIOE3/PWM1A 2 35 GPIOE2/PWM1B 3 34 GPIOE1/PWM0A 4 33 GPIOE0/PWM0B 5 32 VDD 6 31 VSS 7 30 GPIOC12/CANRX0/SDA1/RXD1 8 29 GPIOC11/CANTX0/SCL1/TXD1 9 28 GPIOF0/XB_IN6 10 27 GPIOC10/MOSI/XB_IN5/MISO 11 26 GPIOC9/SCLK/XB_IN4 12 25 GPIOC8/MISO/RXD0 Freescale Semiconductor ...

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... GPIOD2/TCK GPIOD4/RESET GPIOC0/XTAL/CLKIN GPIOC1/EXTAL GPIOC2/TXD0/TB0/XB_IN2/CLKO GPIOF8/RXD0/TB1 GPIOC3/TA0/CMPA_O/RXD0 GPIOC4/TA1/CMPB_O GPIOA7/ANA7 GPIOA6/ANA6 GPIOA5/ANA5 GPIOA4/ANA4 GPIOA0/ANA0/CMPA_P2/CMPC_O GPIOA1/ANA1/CMPA_M0 GPIOA2/ANA2/VREFHA/CMPA_M1 GPIOA3/ANA3/VREFLA/CMPA_M2 Figure 5. Top View: 56F8247 and 56F8257 64-Pin LQFP Package MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor Signal/Connection Descriptions 48 GPIOE3/PWM1A 47 GPIOE2/PWM1B 46 GPIOE1/PWM0A 45 GPIOE0/PWM0B 44 VDD 43 VSS 42 GPIOF5/RXD1/XB_OUT5 ...

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... Schmitt-trigger input is used for noise immunity. Input/ Port D GPIO — This GPIO pin can be individually programmed as Output an input or output pin. After reset, the default state is TCK Signal Description to stabilize the core voltage regulator output Section 8.2, “Electrical on page 73. Freescale Semiconductor ...

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... CMPA_P2) (CMPC_O) GPIOA1 (ANA1& CMPA_M0) MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor State Type During Reset input Input, Test Mode Select Input — This input pin is used to sequence the internal JTAG TAP controller’s state machine sampled on the rising pullup edge of TCK and has an on-chip pullup resistor ...

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... After reset, the default state is GPIOA6. Input/ Input, Port A GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup Input enabled ANA7 — Analog input to channel 7 of ADCA. After reset, the default state is GPIOA7. Signal Description Freescale Semiconductor ...

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... VREFHB& CMPC_P2) GPIOB3 (ANB3& VREFLB& CMPC_M0) MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor State Type During Reset Input/ Input, Port B GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup Input enabled ANB0 and CMPB_P2 — Analog input to channel 0 of ADCB and positive input 2 of analog comparator B ...

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... Port C GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup Analog enabled EXTAL — External Crystal Oscillator Input. This input connects the Input internal crystal oscillator input to an external crystal or ceramic resonator. After reset, the default state is GPIOC1. Signal Description 1 Freescale Semiconductor ...

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... GPIOC4 (TA1) (CMPB_O) GPIOC5 (DACO) (XB_IN7) MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor State Type During Reset Input/ Input, Port C GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup Output enabled TXD0 — The SCI0 transmit data output or transmit/receive in single wire operation ...

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... SCLK — The SPI serial clock. In master mode, this pin serves as Output an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. Input XB_IN4 — Crossbar module input 4 After reset, the default state is GPIOC9. Signal Description Freescale Semiconductor ...

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... Open-drain (RXD1) GPIOC13 (TA3) (XB_IN6) MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor State Type During Reset Input/ Input, Port C GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup Input/ enabled MOSI — Master out/slave in. In master mode, this pin serves as the Output data output ...

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... After reset, the default state is GPIOE2. Input/ Input, Port E GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup Output enabled PWM1A — NanoEdge PWM submodule 1 output A After reset, the default state is GPIOE3. Signal Description Freescale Semiconductor ...

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... GPIOE6 53 (PWM3B) (XB_IN4) GPIOE7 54 (PWM3A) (XB_IN5) GPIOF0 28 36 (XB_IN6) MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor State Type During Reset Input/ Input, Port E GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup Output enabled PWM2B — NanoEdge PWM submodule 2 output B Input XB_IN2 — ...

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... Port F GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup Output enabled RXD1 — The SCI1 receive data input. Output XB_OUT5 — Crossbar module output 5 After reset, the default state is GPIOF5. Signal Description 2 C1 serial clock serial data line. Freescale Semiconductor ...

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... Data address space, including the EOnCE memory and peripheral memory maps On-chip memory sizes for the device are summarized in Restrictions” column of Table 6. MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor State Type During Reset Input/ Input, Port F GPIO — This GPIO pin can be individually programmed as ...

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... Boot location = 0x00 0000 1 for 56F82447 at Reset Memory Allocation RESERVED 2 On-chip RAM : 8 KB • Internal program flash • Interrupt vector table locates from 0x00 2000 to 0x00 2085 • COP reset address = 0x00 2002 • Boot location = 0x00 2000 RESERVED Use Restrictions Figure 6. Freescale Semiconductor ...

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... X:0x00 8FFF X:0x00 8000 X:0x00 7FFF X:0x00 1000 X:0x00 0FFF X:0x00 0000 1 All addresses are 16-bit word addresses. MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor 1 for 56F8245/46 at Reset Memory Allocation RESERVED 2 On-chip RAM : 6 KB • Internal program flash • Interrupt vector table locates from 0x00 2000 to 0x00 2085 • ...

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... Peripherals 0x00 F000 Reserved 0x00 9000 RAM Alias 0x00 8000 Reserved 0x00 1000 RAM 0x00 0000 Data EOnCE 0xFF FF00 Reserved 0x01 0000 Peripherals 0x00 F000 Reserved 0x00 9000 RAM Alias 0x00 8000 Reserved 0x00 1000 RAM 0x00 0000 Freescale Semiconductor ...

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... The 56F825x’s startup address is located at 0x00 0000. The reset value of VBA is reset to a value of 0x0000 that corresponds to the address 0x00 0000. MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor Table 11. 56F8245/56 Data Memory Map Memory Allocation EOnCE 256 locations allocated ...

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... X:0x00 F150 GPIOC X:0x00 F160 GPIOD X:0x00 F170 GPIOE X:0x00 F180 GPIOF X:0x00 F190 DAC X:0x00 F1A0 CMPA X:0x00 F1B0 CMPB X:0x00 F1C0 CMPC X:0x00 F1D0 QSCI0 X:0x00 F1E0 QSCI1 X:0x00 F1F0 QSPI X:0x00 F200 X:0x00 F210 X:0x00 F220 Freescale Semiconductor ...

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... X:0xFF FF9F–X:0xFF FF9E X:0xFF FF9D X:0xFF FF9C X:0xFF FF9B X:0xFF FF9A X:0xFF FF99–X:0xFF FF98 X:0xFF FF97–X:0xFF FF96 X:0xFF FF95–X:0xFF FF94 X:0xFF FF93–X:0xFF FF92 MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor Prefix CRC REFA REFB REFB eFlexPWM FM 1 MSCAN Table 13 Table 13 ...

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... Reserved OBCNTR EOnCE Breakpoint Unit Counter Reserved Reserved Reserved OESCR External Signal Control Register Reserved and V are also the voltage reference high and voltage reference low inputs, SSA Table 5 on page Register Name and V pins as is practical DDA SSA 18. Freescale Semiconductor ...

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... MHz to 16 MHz. A ceramic resonator can be substituted for the 4 MHz to 16 MHz range. When used to supply a source to the internal PLL, the recommended crystal/resonator is in the 8 MHz to 16 MHz range to optimize PLL performance. Oscillator circuits appear in MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor General System Control Information Figure 9 and Figure 10 ...

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... The external clock input must be generated using a relatively low-impedance driver with a maximum frequency not greater than 120 MHz. MC56F825x/MC56F824x Digital Signal Controller, Rev and feedback resistor ( MC56F825x/MC56F824x XTAL EXTAL MC56F825x/MC56F824x XTAL EXTAL Figure 11. The external clock source is connected to the ) are required. In addition, a series F Table 27. 2 Freescale Semiconductor ...

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... Stop/wait mode control • System status control • Registers containing the JTAG ID of the chip • Controls for programmable peripheral and GPIO connections MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor General System Control Information MC56F825x/MC56F824x CLKIN External Clock ( 120 MHz) 39 ...

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... DAC can be internally fed to each comparator’s positive input 1 (CMPn_P1) or negative input 3 (CMPn_M3). In addition, all three comparators’ positive input 3 (CMPn_P3) can be connected together to package pin CMP_REF. Other inputs can be routed to package pins when the corresponding pin is configured for peripheral mode in the GPIO module. MC56F825x/MC56F824x Digital Signal Controller, Rev Table 5 Freescale Semiconductor ...

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... Comparator Input P0 (from internal) 5-bit VREFA_DAC P1 (from internal) 12-bit DAC P2 (from package pin) CMPA_P2 P3 (from package pin) CMP_REF MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor Comparator A Comparator B 5-bit VREFB_DAC 12-bit DAC CMPB_P2 CMP_REF General System Control Information Comparator B 5-bit VREFC_DAC 12-bit DAC ...

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... For example, the user can define an XB_INn pin as a PWM fault protection input that is routed to the PWM module through the crossbar, increasing the flexibility of pin use and reducing the complexity of PCB layout. MC56F825x/MC56F824x Digital Signal Controller, Rev Comparator A Comparator B CMPB_M0 CMPB_M1 CMPB_M2 12-bit DAC Comparator B CMPC_M0 CMPC_M1 CMPC_M2 12-bit DAC Freescale Semiconductor ...

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... DAC DAC0 DAC0 SYNC_IN SYNC_IN VSS VSS VDD VDD 5.7.2.1 Crossbar Switch Inputs Table 15 lists the signal assignments of Crossbar Switch inputs. MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor XBAR_OUT20 XBAR_OUT20 XBAR_OUT21 XBAR_OUT21 XBAR_OUT22 XBAR_OUT22 XBAR_OUT23 XBAR_OUT23 XBAR_OUT24 XBAR_OUT24 XBAR_OUT25 XBAR_OUT25 XBAR_OUT15 ...

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... Quad Timer B3 Output eFlexPWM submodule 0: PWM0_OUT_TRIG0 or PWM0_OUT_TRIG1 eFlexPWM submodule 1: PWM1_OUT_TRIG0 or PWM1_OUT_TRIG1 eFlexPWM submodule 2: PWM2_OUT_TRIG0 or PWM2_OUT_TRIG1 eFlexPWM submodule PWM0_TRIG_COMB or PWM1_TRIG_COMB or PWM2_TRIG_COMB eFlexPWM submodule 3: PWM3_OUT_TRIG0 eFlexPWM submodule 3: PWM3_OUT_TRIG1 Function Package pin Package pin Package pin Package pin Package pin Package pin ADCA Trigger Freescale Semiconductor ...

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... PWM0_EXTB is driven high. State of PWM1_EXTB: • If the ADC conversion result in SAMPLE1 is greater than the value programmed into the high limit register 1, PWM1_EXTB is driven low. MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor General System Control Information Function ADCB Trigger 12-bit DAC SYNC_IN Comparator A Window/Sample ...

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... After you have programmed flash with the application code part of programming the flash with the application code, you can secure the MC56F825x/MC56F824x by programming the values 1 and 0 into bits 1 and 0, respectively, of program memory location 0x00_7FF7. The CodeWarrior IDE menu flash lock command can also accomplish this task. The nonvolatile security MC56F825x/MC56F824x Digital Signal Controller, Rev NOTE Freescale Semiconductor ...

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... You can accomplish the same task with another CodeWarrior mechanism that uses the device’s memory configuration file: the command “Unlock_Flash_on_Connect 1” in the .cfg file. This lockout recovery mechanism completely erases the internal flash contents, including the configuration field, thereby disabling security (the protection register is cleared). MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor NOTE Security Features 47 ...

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... Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. MC56F825x/MC56F824x Digital Signal Controller, Rev NOTE Unit.” The customer must supply technical-support details about the protocol CAUTION Section 6.2.4.2, Freescale Semiconductor ...

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... Pin Group 1: GPIO, TDI, TDO, TMS, TCK Pin Group 2: RESET, GPIOA7 Pin Group 3: ADC and Comparator Analog Inputs Pin Group 4: XTAL, EXTAL Pin Group 5: DAC analog output MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor CAUTION Table 17 may affect device reliability or cause = 3 3 < ...

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... Single layer board R JA (1s) Four layer board R JMA (2s2p) Single layer board R JMA (1s) Four layer board R JMA (2s2p Natural convection JT Max Unit — V — V — power calculations, determine the I very small Value Unit (LQFP) 70 °C/W 48 °C/W 57 °C/W 42 °C/W 30 °C/W 13 °C/W 2 °C/W Freescale Semiconductor ...

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... Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51–2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor Comments Symbol Single layer board ...

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... V) SSA SS Min Typ Max 3 3.3 3.6 3.0 V DDA -0.1 0 0.1 -0.1 0 0.1 0.001 2.0 5.5 -0.3 0.8 2 0.3 DD -0.3 0.8 3K 400 — -4 — -8 — 4 — 8 -40 105 10,000 — 15 — 20 — — Freescale Semiconductor Unit MHz °C cycles years years ...

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... Pin Group 2: RESET, GPIOA7 Pin Group 3: ADC and Comparator Analog Inputs Pin Group 4: XTAL, EXTAL Pin Group 5: DAC analog output 7.6 DC Electrical Characteristics This section includes information about power supply requirements and I/O pin characteristics. MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor Specifications 53 ...

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... Conditions — — — 0 +/- 2 +/- +/- -30 -60 0 +/- 2.5 110 220 k 0 +/- +/- 2 A — Typically – DDA +/- 2.5 A 0.35 — — — pF 3.5 4.0 4.5 5.0 5.5 Freescale Semiconductor Test = I OHmax = I OLmax = 2 5 DDA = V IN DDA — — — — — — 6.0 ...

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... All peripheral module and core clocks are off ADC /DAC/comparator powered off Voltage regulator in standby mode 1 No output switching All ports configured as inputs All inputs low No DC loads MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor Table 24. Current Consumption Conditions I 0.76 0.66 Specifications Typical @ 3.3 V Maximum @ 3.6 V 25° ...

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... Unless otherwise specified, propagation delays are measured Low The midpoint – Typ Max Unit 2.6 2.7 2.8 V — 2.18 — V — 50 — mV 2.6 2.7 2.8 V — 1.8 1.9 V Typical Max Unit 900 1300 mA — 30 minutes High 90% 50% 10% Rise Time )/2. Freescale Semiconductor Figure 15. ...

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... Specifies page erase time. There are 1024 bytes per page in the program flash memory. 7.13 External Clock Operation Timing Table 29. External Clock Operation Timing Requirements Characteristic Frequency of operation (external clock driver) Clock pulse width MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor Data2 Valid Data2 Data Three-stated Figure 16 ...

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... Max — — 3 — — 3 — — DD — — 0.3V DD 90% 50% 10 fall rise Symbol Min Typ Max ref f 120 — 240 op t — 40 100 plls J — — TBD A t — 350 — jitterpll Freescale Semiconductor Unit Unit MHz MHz µ ...

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... J is required to meet QSCI requirements See Figure 18. 8.16 8.08 8 7.92 7.84 -50 -25 Figure 18. Relaxation Oscillator Temperature Variation (Typical) After Trim MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor Table 31. Crystal or Resonator Requirement Symbol Min f XOSC Table 32. Relaxation Oscillator Timing Symbol Minimum roscs t ...

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... Typical Max Unit See Figure — ns — — ns Figure 19 97T + 65T ns — OSC 6T ns — Max Unit Refer to Figure 20, — ns Figure 21, — ns Figure 22, Figure 23 Figure 23 — ns — ns Figure 23 — ns — ns Figure 20, — ns Figure 21, — ns Figure 22, Figure 23 Figure 23 — ns — ns Freescale Semiconductor ...

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... Slave Data valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave 1 Parameters listed are guaranteed by design. MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor 1 Table 34. SPI Timing (continued) Symbol Min 4.8 ...

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... DI Master MSB out Bits 14– Figure 20. SPI Master Timing (CPHA = held High on master MSB in Bits 14– Master MSB out Bits 14– Figure 21. SPI Master Timing (CPHA = LSB in t (ref Master LSB out LSB (ref Master LSB out t R Freescale Semiconductor ...

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... SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input MISO (Output MOSI (Input) MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor ELD Slave MSB out Bits 14– MSB in Bits 14–1 Figure 22. SPI Slave Timing (CPHA = 0) ...

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... TOL_SYNCH T 13 BREAK 11 RXD PW Figure 24. RXD Pulse Width TXD PW Figure 25. TXD Pulse Width Max Unit See Figure (f /16) Mbps — MAX 1.04/BR ns Figure 24 1.04/BR ns Figure — — — Master node — bit periods — Slave node — bit periods Freescale Semiconductor ...

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... This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line 1000 + 250 = 1250 ns (according to the Standard mode I rmax SU; DAT MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor Table 36. MSCAN Timing Symbol BR CAN T T WAKEUP ...

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... SU; STA SR t HIGH Table 38. JTAG Timing Symbol Min Max f DC SYS_CLK — — Figure 28. Test Clock Input Timing Diagram HD; STA SP t SU; STO Bus Unit See Figure MHz Figure 28 — ns Figure 28 — ns Figure 29 — ns Figure Figure Figure Freescale Semiconductor t BUF S ...

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... Timer input high/low period Timer output period Timer output high/low period 1 In the formulas listed the clock cycle. For 32 MHz operation 31.25 ns. 2. Parameters listed are guaranteed by design. Timer Inputs Timer Outputs MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor t DS Input Data Valid Table 39 ...

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... Hz TBD nA Max Unit 12 Bits 15 MHz V V REFH — cycles AIC — cycles AIC mA — — — — — cycles AIC — cycles AIC 4 +/- 6 6 LSB +/- 1 5 LSB +/- 15 mV +/- 15 mV 1.01 to 0.99 — REFH V V DDA +/- 2 A — — pF Freescale Semiconductor ...

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... described in note 4 below. gain Analog input 125-ohm ESD resisto Parasitic capacitance due to package, pin-to-pin, and pin-to-package base coupling: 1.8 pF MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor 1 Table 41. ADC Parameters (continued) Symbol Min X — MHz) ADC SNR — ...

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... Min Typ Max 12 — 12 TBD — 2 — — 11 — +/- 3 +/- 8.0 — +/- 0.8 +/- 1.0 guaranteed — +/- 25 +/- 40 — +/- .5 +/- 1.5 — V REFLX REFHX - 0.04V — TBD — — TBD — — — — Freescale Semiconductor Unit bits µS µS 2 LSB 2 LSB — Bits ...

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... Total power = A, the internal [static] component, consists of the DC bias currents for the oscillator, leakage currents, PLL, and voltage references. These sources operate independently of processor state or operating frequency. MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor or V DDA SSA Table 43. 5-Bit DAC Specifications ...

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... I/O cells as a function of Equation 2 applies. )*frequency/10 MHz) load , can be obtained from Equation Ambient temperature for the package ( A = Junction-to-ambient thermal resistance ( J = Power dissipation in the package (W) D Slope 0.11 mW/pF 0.11 mW/ C/W) Freescale Semiconductor Eqn Eqn. 3 ...

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... This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, take normal precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor ...

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... To eliminate PCB trace impedance effect, each ADC input should have an RC filter of no less than • External clamp diodes on analog input pins are recommended. 9 Ordering Information Table 46 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order devices. MC56F825x/MC56F824x Digital Signal Controller, Rev (GND) pin. SS ...

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... C MC56F8247VLH –40° 125° C MC56F8247MLH 60 –40° 105° C MC56F8255VLD –40° 125° C MC56F8255MLD 60 –40° 105° C MC56F8256VLF –40° 125° C MC56F8256MLF 60 –40° 105° C MC56F8257VLH –40° 125° C MC56F8257MLH 1 75 ...

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... Package Mechanical Outline Drawings To ensure you have the latest version of a package drawing www.freescale.com and perform a keyword search for the drawing’s document number (shown in the following sections for each package). 10.1 44-pin LQFP MC56F825x/MC56F824x Digital Signal Controller, Rev Freescale Semiconductor ...

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... MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor Package Mechanical Outline Drawings 77 ...

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... Package Mechanical Outline Drawings Figure 32. 56F8245 and 56F8255 44-Pin LQFP Mechanical Information MC56F825x/MC56F824x Digital Signal Controller, Rev Freescale Semiconductor ...

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... LQFP MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor Package Mechanical Outline Drawings 79 ...

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... Package Mechanical Outline Drawings Figure 33. 56F8246 and 56F8256 48-Pin LQFP Mechanical Information MC56F825x/MC56F824x Digital Signal Controller, Rev Freescale Semiconductor ...

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... LQFP MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor Package Mechanical Outline Drawings 81 ...

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... Package Mechanical Outline Drawings MC56F825x/MC56F824x Digital Signal Controller, Rev Freescale Semiconductor ...

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... Figure 34. 56F8247 and 56F8257 64-Pin LQFP Mechanical Information MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor Package Mechanical Outline Drawings 83 ...

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... Table 47. Revision History Description 75: Added “M” orderable part numbers 55: Updated data for run, wait, and stop modes, and added data for standby and 54: Added minimum and maximum values for Internal Pull-Up Resistance Section 9 (was 8.3), Section 10 (was 9), Section 11 (was 10) Freescale Semiconductor ...

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... TMRB0 ADCB_CC ADCA_CC ADC_Err CAN CAN MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor Table 48. Interrupt Vector Table Contents Vector Base Address + P:0x00 P:0x02 Reserved for COP Reset Overlay 3 P:0x04 3 P:0x06 3 P:0x08 3 P:0x0A P:0x0C P:0x0E P:0x10 P:0x12 EOnCE Transmit Register Empty P:0x14 ...

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... P:0x68 PWM Sub-Module 0 Reload P:0x6A PWM Sub-Module 0Compare P:0x6C Flash Memory Access Error P:0x6E Flash Memory Programming Command Complete P:0x70 Flash Memory Buffer Empty Request P:0x72 Comparator C Rising/Falling Flag P:0x74 Comparator B Rising/Falling Flag 2 C1 Interrupt 2 C0 Interrupt PWM Fault Freescale Semiconductor ...

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... If the VBA is set to the reset value, the first two locations of the vector table overlay the chip reset addresses because the reset address would match the base of this vector table. MC56F825x/MC56F824x Digital Signal Controller, Rev. 3 Freescale Semiconductor Vector Base Address + P:0x76 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...