AM3517AZER

Manufacturer Part NumberAM3517AZER
DescriptionIC ARM8 CORTEX MCU 484BGA
ManufacturerTexas Instruments
SeriesSitara ARM®, Cortex™A8, ARM9
AM3517AZER datasheet
 

Specifications of AM3517AZER

Processor TypeARM MicroprocessorSpeed600MHz
Voltage1.2VMounting TypeSurface Mount
Package / Case484-BBGA Exposed PadLead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names296-28243
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AM3517/05 Sitara ARM Microprocessors
1 AM3517/05 Sitara ARM Microprocessor
1.1
Features
12345678
• AM3517/05 Sitara ARM Microprocessor:
– MPU Subsystem
®
600-MHz Sitara™ ARM
TM
NEON
SIMD Coprocessor and Vector
floating point (FP) co-processor
– Memory Interfaces:
166 MHz 16/32- bit mDDR/DDR2 Interface
with 1 GByte total addressable space
Up to 83 MHz General Purpose Memory
Interface supporting 16-bit Wide
Multiplexed Address/Data bus
64 K-Byte SRAM
3 Removable Media Interfaces
[MMC/SD/SDIO]
– IO Voltage:
mDDR/DDR2 IOs: 1.8V
Other IOs: 1.8V and 3.3V
– Core Voltage: 1.2V
– Commercial and ExtendedTemperature
Grade
(operating restrictions apply)
– 16-bit Video Input Port capable of capturing
HD video
– HD resolution Display Subsystem
– Serial Communication
High-End CAN Controller
10/100 Mbit Ethernet MAC
USB OTG subsystem with standard
DP/DM interface [HS/FS/LS]
Multiport USB Host Subsystem
[HS/FS/LS]
– 12-pin ULPI or 6/4/3-pin Serial
Interface
Four Master/Slave Multichannel Serial
Port Interface (McSPI) Ports
Five Multichannel Buffered Serial Ports
– 512-Byte Transmit/Receive Buffer
(McBSP1/3/4/5)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
POWERVR SGX is a trademark of Imagination Technologies Ltd.
2
Sitara is a trademark of Texas Instruments.
3
Cortex is a trademark of ARM Limited.
4
NEON, Jazelle are registered trademarks of ARM Limited.
5
ARM is a registered trademark of ARM Physical IP, Inc..
6
Android is a trademark of Google Inc..
7
All other trademarks are the property of their respective owners.
8
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Check for Samples: AM3517,
AM3505
Cortex™-A8 Core
• Display subsystem
– Parallel Digital Output
– Up to 24-Bit RGB
– Supports Up to 2 LCD Panels
– Support for Remote Frame Buffer Interface
(RFBI) LCD Panels
– Two 10-bit Digital-to-Analog Converters
(DACs) Supporting
– Rotation 90, 180, and 270 degrees
– Resize Images From 1/4x to 8x
– Color Space Converter
– 8-bit Alpha Blending
• Video Processing Front End (VPFE) 16-bit
Video Input Port
– RAW Data Interface
– 75-MHz Maximum Pixel Clock
– Supports REC656/CCIR656 Standard
AM3517, AM3505
SPRS550C – OCTOBER 2009 – REVISED MARCH 2011
– 5K-Byte Transmit/Receive Buffer
(McBSP2)
– SIDETONE Core Support (McBSP2 and
3 Only) For Filter, Gain, and Mix
Operations
– 128-Channel Transmit/Receive Mode
– Direct Interface to I2S and PCM Device
and TDM Buses
HDQ/1-Wire Interface
4 UARTs (One with Infrared Data
Association [IrDA] and Consumer Infrared
[CIR] Modes)
3 Master/Slave High-Speed
Inter-Integrated Circuit (I2C) Controllers
12 32-bit General Purpose Timers
1 32-bit Watchdog Timer
1 32-bit 32-kHz Sync Timer
Up to 186 General-Purpose I/O (GPIO)
Pins
Composite NTSC/PAL Video
Luma/Chroma Separate Video (S-Video)
Copyright © 2009–2011, Texas Instruments Incorporated

AM3517AZER Summary of contents

  • Page 1

    ... Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. POWERVR SGX is a trademark of Imagination Technologies Ltd. 2 Sitara is a trademark of Texas Instruments. 3 Cortex is a trademark of ARM Limited. 4 NEON, Jazelle are registered trademarks of ARM Limited ...

  • Page 2

    ... Point of Service – Portable Media Player – Portable Industrial – Transportation – Navigation – Smart White Goods – Digital TV – Digital Video Camera – Gaming Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com ...

  • Page 3

    ... AM3517/05 devices are available in a 491-pin BGA package and a 484-pin PBGA package. This AM3517/05 data manual presents the electrical and mechanical specifications for the AM3517/05 Sitara ARM Microprocessor Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 . ...

  • Page 4

    ... AM3517/05 Sitara CVBS or S-Video USB transceivers / device ports [3] Analog DAC HS/FS/ LS USB USB PHY Host USB OTG Controller 32 VPFE 32 L4 Interconnect Peripherals: System Controls 5xMcBSP PRCM HDQ/1 Wire, External Peripherals Interfaces Emulation SPRS550-006 Copyright © 2009–2011, Texas Instruments Incorporated ARM ...

  • Page 5

    ... ZER and ZCN package differences on the device. Table 1-1. ZCN and ZER Package Differences FEATURE Pin Assignments Video Interfaces Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 ZCN PACKAGE For ZCN package pin assignments, see Terminal Description ...

  • Page 6

    ... Copyright © 2009–2011, Texas Instruments Incorporated 97 100 101 102 104 105 106 106 106 107 108 150 155 196 210 214 214 ...

  • Page 7

    ... Added table note Characteristics • Table 6-130 – Moved all time entries from max to min column Copyright © 2009–2011, Texas Instruments Incorporated Revision History ADDITIONS/MODIFICATIONS/DELETIONS Ball Characteristics (ZCN Pkg.) Ball Characteristics (ZER Pkg.) Serial Communication Interfaces - UARTs Signals Description Removable Media Interfaces - MMC/SDIO Signals Description ...

  • Page 8

    ... The following illustrations show the top views of the 484-pin [ZER] and 491-pin [ZCN] package pin assignments in four quadrants ( and D). Note: A pin with an "NC" designator indicates No Connection. For proper device operation, these pins must be left unconnected. 8 TERMINAL DESCRIPTION Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com ...

  • Page 9

    ... MCBSP_ MCBSP1_ MCBSP1_ MCBSP1_ CLKS FSX SYS_ MCBSP1_ VSS NC CLKOUT1 CLKX M SYS_ SYS_ CLKOUT2 CLKREQ Copyright © 2009–2011, Texas Instruments Incorporated ETK_D12 ETK_D8 ETK_D5 ETK_CTL ETK_D13 ETK_D9 ETK_D6 ETK_D0 ETK_D14 ETK_D10 ETK_D1 ETK_D11 ETK_D7 ETK_D2 UART1_TX ETK_D3 UART1_CTS UART1_RTS ETK_D4 ...

  • Page 10

    ... WAIT1 WAIT0 NBE1 GPMC_NBE0 GPMC_NADV GPMC_ GPMC_ VDDS _CLE _ALE NWE NOE UART3_RX UART3_TX _IRRX _IRTX GPMC_ GPMC_ UART3_RTS UART3_CTS GPMC_CLK NCS6 NCS7 _SD _RCTX GPMC_ GPMC_ GPMC_ GPMC_ VDDSHV NCS2 NCS3 NCS4 NCS5 Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 11

    ... MCBSP3_ MCBSP3_ C CLKX DR FSX MCBSP4_ MCBSP4_ B MCBSP2_DR MCBSP3_DX CLKX DX MCBSP3_ MCBSP4_ MCBSP4_ A VSS CLKX DR FSX Copyright © 2009–2011, Texas Instruments Incorporated VDDSHV VDD_CORE NC VDDSOSC TV_ VDDSHV VDD_CORE VDD_CORE TV_VFB1 OUT1 VSS VDDSHV NC VDDSHV VDDA_DAC TV_VREF VSS VSS UART2_CTS UART2_RTS VDDS_SRAM ...

  • Page 12

    ... GPMC_D6 GPMC_D0 GPMC_D1 GPMC_D2 GPMC_D3 GPMC_D4 GPMC_A8 GPMC_A9 GPMC_A6 GPMC_A7 GPMC_A1 GPMC_A2 GPMC_A3 SDRC_DM3 SCRC_D29 SDRC_D23 SDRC_D27 SDRC_D28 SDRC_D31 SDRC_ SDRC_D30 SDRC_D22 SDRC_D26 SDRC_24 DQS3N SDRC_ SDRC_ SDRC_ SDRC_D25 VSS STRBEN DQS3P STRBEN1 _DLY1 Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 13

    ... DSS_DATA10 DSS_DATA11 16 DSS_DATA16 DSS_DATA15 DSS_DATA19 DSS_DATA14 15 14 DSS_DATA17 DSS_DATA23 DSS_DATA22 DSS_DATA12 DSS_DATA20 DSS_DATA21 DSS_DATA18 JTAG_NTRST JTAG_EMU0 13 JTAG_TMS_ 12 JTAG_TDI JTAG_RTCK JTAG_TDO TMSC Copyright © 2009–2011, Texas Instruments Incorporated MCSPI2_ ETK_D10 ETK_D1 ETK_CLK SOMI ETK_D7 ETK_D5 ETK_CTL MCSPI2_CS0 MCSPI1_CS3 MCSPI2_ ETK_D11 ETK_D2 ...

  • Page 14

    ... SYS_BOOT0 19 SYS_NRE SYS_NRES SYS_NIRQ 18 SWARM PWRON I2C3_SDA I2C2_SCL I2C1_SCL I2C1_SDA 17 GPMC_ I2C3_SCL I2C2_SDA HECC1_RXD 16 WAIT1 UART3_CTS GPMC_NBE1 GPMC_NWE HECC1_TXD 15 _RCTX GPMC_ GPMC_ GPMC_NWP GPMC_NOE 14 WAIT2 NADV_ALE UART3_RTS UART3_TX UART3_RX GPMC_CLK 13 _SD _IRTX _IRRX VSS Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 15

    ... UART2_RTS MCBSP2_DR 5 MCBSP3 MCBSP3_FSX MCBSP3_DR MCBSP3_DX 4 MCBSP4 MCBSP4_DR SDRC_D2 SDRC_D1 3 _CLKX 2 MCBSP4_DX MCBSP4_FSX SDRC_D3 SDRC_D5 1 VSS VDDSHV SDRC_D6 SDRC_D7 Copyright © 2009–2011, Texas Instruments Incorporated VDDS_ DPLL_PER VSS VSS _CORE SYS_ NC NC VDDSHV VSS CLKOUT2 SYS_ VSS NC VDDSOSC NC CLKOUT1 VDDSHV ...

  • Page 16

    ... GPMC_D7 8 GPMC_D2 GPMC_D1 GPMC_D0 GPMC_A9 7 GPMC_A8 GPMC_A10 GPMC_A7 GPMC_A6 6 GPMC_A1 GPMC_A2 GPMC_A4 GPMC_A5 5 SDRC_D25 SDRC_D27 SDRC_D30 GPMC_A3 4 SDRC_D24 SDRC_D26 SDRC_D29 SDRC_DM3 3 SDRC_ STRBEN SDRC_ SDRC_D28 SDRC_D31 2 _DLY1 DQS3N SDRC_ SDRC_ VDDS VSS 1 STRBEN1 DQS3P Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 17

    ... HYS: Indicates if the input buffer is with hysteresis. 11. LOAD: Load capacitance of the associated output buffer. 12. PULL U/D - TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software. Copyright © 2009–2011, Texas Instruments Incorporated Section (pulldown/pullup resistor not activated) OL with an active pulldown resistor ...

  • Page 18

    ... PU PU PU PU PU PU PU/ PD Copyright © 2009–2011, Texas Instruments Incorporated IO CELL [13] LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS ...

  • Page 19

    ... O gpio_39 4 IO safe_mode 7 F3 gpmc_a7 0 O gpio_40 4 IO safe_mode 7 F2 gpmc_a8 0 O gpio_41 4 IO safe_mode 7 F1 gpmc_a9 0 O Copyright © 2009–2011, Texas Instruments Incorporated BALL BALL RESET REL. POWER [8] RESET RESET REL. MODE [7] STATE [5] STATE [ VDDS VDDS VDDS VDDS L ...

  • Page 20

    ... PU/ PD 1.8V/3. 1.8V/3.3V Yes 30 PU/ PD 1.8V/3.3V Yes 30 PU/ PD 1.8V/3.3V Yes 30 PU/ PD 1.8V/3.3V Yes 30 PU/ PD Copyright © 2009–2011, Texas Instruments Incorporated IO CELL [13] LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS ...

  • Page 21

    ... IO safe_mode 7 AE23 dss_pclk 0 O gpio_66 4 IO hw_dbg12 5 O safe_mode 7 AD22 dss_hsync 0 O gpio_67 4 IO hw_dbg13 5 O safe_mode 7 Copyright © 2009–2011, Texas Instruments Incorporated BALL BALL RESET REL. POWER [8] RESET RESET REL. MODE [7] STATE [5] STATE [ VDDSHV VDDSHV VDDSHV VDDSHV L ...

  • Page 22

    ... Yes 20 PU/ PD 1.8V/3.3V Yes 20 PU/ PD 1.8V/3.3V Yes 20 PU/ PD 1.8V/3.3V Yes 20 PU/ PD 1.8V/3.3V Yes 20 PU/ PD 1.8V/3.3V Yes 20 PU/ PD Copyright © 2009–2011, Texas Instruments Incorporated IO CELL [13] LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS ...

  • Page 23

    ... O K20 tv_vfb1 0 O H23 tv_vfb2 0 O H20 tv_vref 0 I AD2 ccdc_pclk 0 IO gpio_94 4 IO hw_dbg0 5 O safe_mode 7 Copyright © 2009–2011, Texas Instruments Incorporated BALL BALL RESET REL. POWER [8] RESET RESET REL. MODE [7] STATE [5] STATE [ VDDSHV VDDSHV VDDSHV VDDSHV ...

  • Page 24

    ... Yes 15 PU/ PD 1.8V/3.3V Yes 15 PU/ PD 1.8V/3.3V Yes 15 PU/ PD 1.8V/3.3V Yes 15 PU/ PD 1.8V/3.3V Yes 15 PU/PD 1.8V/3.3V Yes 15 PU/PD 1.8V/3.3V Yes 25 PU/PD Copyright © 2009–2011, Texas Instruments Incorporated IO CELL [13] LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS ...

  • Page 25

    ... IO safe_mode 7 B25 mcbsp2_dr 0 I gpio_118 4 IO safe_mode 7 D24 mcbsp2_dx 0 IO gpio_119 4 IO safe_mode 7 AA9 mmc1_clk 0 O gpio_120 4 IO Copyright © 2009–2011, Texas Instruments Incorporated BALL BALL RESET REL. POWER [8] RESET RESET REL. MODE [7] STATE [5] STATE [ VDDSHV VDDSHV VDDSHV VDDSHV H ...

  • Page 26

    ... No 30 PU/ PD 1.8V/3. PU/ PD 1.8V/3.3V Yes 30 PU/ PD 1.8V/3.3V Yes 30 PU/ PD 1.8V/3.3V Yes 30 PU/ PD 1.8V/3.3V Yes 30 PU/ PD 1.8V/3.3V Yes 30 PU/ PD Copyright © 2009–2011, Texas Instruments Incorporated IO CELL [13] LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS ...

  • Page 27

    ... IO uart2_rx 1 I gpio_143 4 IO safe_mode 7 F20 uart2_cts 0 I mcbsp3_dx 1 IO gpt9_pwm_e gpio_144 4 IO safe_mode 7 F19 uart2_rts 0 O Copyright © 2009–2011, Texas Instruments Incorporated BALL BALL RESET REL. POWER [8] RESET RESET REL. MODE [7] STATE [5] STATE [ VDDSHV VDDSHV VDDSHV VDDSHV L PD ...

  • Page 28

    ... Yes 30 PU/ PD 1.8V/3.3V Yes 30 PU/ PD 1.8V/3.3V Yes 30 PU/ PD 1.8V/3.3V Yes 30 PU/ PD 1.8V/3.3V Yes 30 PU/ PD 1.8V/3.3V Yes 30 PU/ PD 1.8V/3.3V Yes 30 PU/ PD Copyright © 2009–2011, Texas Instruments Incorporated IO CELL [13] LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS ...

  • Page 29

    ... G25 usb0_id 0 A E25 usb0_drvvbu uart3_tx_ irtx 2 O gpio_125 4 IO safe_mode 7 V2 hecc1_ txd 0 O uart3_rx_ irrx 2 I gpio_130 4 IO Copyright © 2009–2011, Texas Instruments Incorporated BALL BALL RESET REL. POWER [8] RESET RESET REL. MODE [7] STATE [5] STATE [ VDDSHV VDDSHV VDDSHV ...

  • Page 30

    ... PU/ PD 1.8V/3.3V Yes 30 PU/ PD 1.8V/3.3V Yes 30 PU/ PD 1.8V/3.3V Yes 30 PU/ PD 1.8V/3.3V Yes 30 PU/ PD Copyright © 2009–2011, Texas Instruments Incorporated IO CELL [13] LVCMOS Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS ...

  • Page 31

    ... IO Y4 sys_boot0 0 I gpio_2 4 IO AA1 sys_boot1 0 I gpio_3 4 IO AA2 sys_boot2 0 I gpio_4 4 IO AA3 sys_boot3 0 I Copyright © 2009–2011, Texas Instruments Incorporated BALL BALL RESET REL. POWER [8] RESET RESET REL. MODE [7] STATE [5] STATE [ VDDSHV VDDSHV VDDSHV VDDSHV L ...

  • Page 32

    ... PU/ PD 1.8V/3.3V Yes 9, 25 PU/ PD 1.8V/3.3V Yes 9, 25 PU/ PD 1.8V/3.3V Yes 9, 25 PU/ PD 1.8V/3.3V Yes 9, 25 PU/ PD Copyright © 2009–2011, Texas Instruments Incorporated IO CELL [13] LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS ...

  • Page 33

    ... IO xdm AC20 etk_d10 0 O uart1_rx 2 I hsusb2_clk 3 O gpio_24 4 IO AB20 etk_d11 0 O mcspi3_clk 1 IO hsusb2_stp 3 O Copyright © 2009–2011, Texas Instruments Incorporated BALL BALL RESET REL. POWER [8] RESET RESET REL. MODE [7] STATE [5] STATE [ VDDSHV VDDSHV VDDSHV L PD ...

  • Page 34

    ... TYPE [12] 1.8V/3.3V Yes 9, 25 PU/ PD 1.8V/3.3V Yes 9, 25 PU/ PD 1.8V/3.3V Yes 9, 25 PU/ PD 1.8V/3.3V Yes 9, 25 PU/ PD 1.2V 1.8V 1.8V 1.2V 1.2V 1.8V 1.8V 1.8V 3.3V 1.8V 1.2V Copyright © 2009–2011, Texas Instruments Incorporated IO CELL [13] LVCMOS LVCMOS LVCMOS LVCMOS ...

  • Page 35

    ... V1 Reserved (2) "NC" indicates "No Connect". For proper device operation, these pins must be left unconnected. (3) For proper device operation, this pin must be pulled up to VDDSHV via a 10k-Ω resistor. Copyright © 2009–2011, Texas Instruments Incorporated BALL BALL RESET REL. POWER [8] RESET RESET REL ...

  • Page 36

    ... VDDS 1. VDDS 1. VDDS 1. VDDS 1. VDDS 1. VDDS 1. VDDS 1.8V Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com HYS [10] LOAD (pF) PULL U/D IO CELL [13] [11] TYPE [12] Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes ...

  • Page 37

    ... H W7 gpmc_d2 AA9 gpmc_d3 gpmc_d4 AA8 gpmc_d5 AB8 gpmc_d6 gpmc_d7 Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 BALL RESET REL. POWER [8] VOLTAGE RESET REL. MODE [7] [9] [5] STATE [ VDDS 1. VDDS 1. VDDS 1. VDDS 1. VDDS 1.8V ...

  • Page 38

    ... VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3.3V Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com HYS [10] LOAD (pF) PULL U/D IO CELL [13] [11] TYPE [12] Yes 30 PU/ PD LVCMOS Yes 30 PU/ PD LVCMOS ...

  • Page 39

    ... B16 dss_data7 uart1_rx 2 I gpio_77 4 IO hw_dbg15 5 O B17 dss_data8 gpio_78 4 IO Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 BALL RESET REL. POWER [8] VOLTAGE RESET REL. MODE [7] [9] [5] STATE [ VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1 ...

  • Page 40

    ... VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3.3V Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com HYS [10] LOAD (pF) PULL U/D IO CELL [13] [11] TYPE [12] Yes 20 PU/ PD LVCMOS Yes 20 PU/ PD LVCMOS ...

  • Page 41

    ... I H ccdc_data13 1 I gpio_167 4 IO hw_dbg10 5 O T22 rmii_txd0 ccdc_ data14 1 I Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 BALL RESET REL. POWER [8] VOLTAGE RESET REL. MODE [7] [9] [5] STATE [ VDDSHV 1.8V/3. VDDSHV 1.8V/3.3V ...

  • Page 42

    ... VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3.3V Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com HYS [10] LOAD (pF) PULL U/D IO CELL [13] [11] TYPE [12] Yes 25 PU/PD LVCMOS 25 PU/PD LVCMOS NA 25 ...

  • Page 43

    ... I gpt10_pwm_ 2 IO evt gpio_145 uart2_tx mcbsp3_clkx 1 IO gpt11_pwm 2 IO _evt Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 BALL RESET REL. POWER [8] VOLTAGE RESET REL. MODE [7] [9] [5] STATE [ VDDSHV 1.8V/3. VDDSHV 1.8V/3.3V ...

  • Page 44

    ... VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3.3V Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com HYS [10] LOAD (pF) PULL U/D IO CELL [13] [11] TYPE [12] Yes 30 PU/ PD LVCMOS Yes 30 PU/ PD LVCMOS ...

  • Page 45

    ... K18 mcspi1_cs0 mmc2_dat7 1 IO gpio_174 4 IO J20 mcspi1_cs1 mmc3_cmd 3 IO gpio_175 4 IO Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 BALL RESET REL. POWER [8] VOLTAGE RESET REL. MODE [7] [9] [5] STATE [ VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1 ...

  • Page 46

    ... VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3.3V Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com HYS [10] LOAD (pF) PULL U/D IO CELL [13] [11] TYPE [12] Yes 30 PU/ PD LVCMOS Yes 30 PU/ PD LVCMOS ...

  • Page 47

    ... IO mm_fsusb1_t 5 IO xse0 F20 etk_d2 mcspi3_cs0 1 IO (1) Mux0 if sys_boot6 is pulled down (clock master). Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 BALL RESET REL. POWER [8] VOLTAGE RESET REL. MODE [7] [9] [5] STATE [ VDDSHV 1 ...

  • Page 48

    ... PD 4 VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3. VDDSHV 1.8V/3.3V Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com HYS [10] LOAD (pF) PULL U/D IO CELL [13] [11] TYPE [12] Yes 9, 25 PU/ PD LVCMOS Yes 9, 25 PU/ PD ...

  • Page 49

    ... F11 VDDS_DPLL 0 PWR _PER_CORE F7 VDDA3P3V_ 0 PWR USBPHY D7 VDDA1P8V_ 0 PWR USBPHY E7 CAP_VDDA1 0 PWR P2LDO_USB PHY Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 BALL RESET REL. POWER [8] VOLTAGE RESET REL. MODE [7] [9] [5] STATE [ VDDSHV 1.8V/3.3V PD ...

  • Page 50

    ... For proper device operation, this pin must be pulled up via a 10k-Ω resistor. 50 TERMINAL DESCRIPTION BALL RESET REL. POWER [8] VOLTAGE RESET REL. MODE [7] [9] [5] STATE [6] 1.8V/3.3V 1. VDDS 1.8V Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com HYS [10] LOAD (pF) PULL U/D IO CELL [13] [11] TYPE [12] ...

  • Page 51

    ... A8 sdrc_a12 R4 B8 sdrc_a13 T2 D8 sdrc_a14 J4 E13 sdrc_ncs0 Copyright © 2009–2011, Texas Instruments Incorporated Table 2-3. Multiplexing Characteristics MODE 2 MODE 3 MODE 4 Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 AM3517, AM3505 SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 MODE 5 MODE 6 ...

  • Page 52

    ... Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com MODE 5 MODE 6 MODE 7 sdrc_cke0_safe safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode ...

  • Page 53

    ... AD4 ccdc_data0 W20 AE4 ccdc_data1 V21 AC5 ccdc_data2 V19 AD5 ccdc_data3 V22 AE5 ccdc_data4 Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 MODE 2 MODE 3 MODE 4 gpt11_pwm_evt gpio_57 gpt8_pwm_evt gpio_58 gpio_59 gpio_60 gpio_61 gpio_62 gpio_63 ...

  • Page 54

    ... Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com MODE 5 MODE 6 MODE 7 hw_dbg7 safe_mode safe_mode safe_mode safe_mode safe_mode hw_dbg8 ...

  • Page 55

    ... E20 AB20 etk_d11 mcspi3_clk E18 AE21 etk_d12 D20 AD21 etk_d13 (1) This mux selection is controlled by CONTROL_DEVCONF2 register. Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 MODE 2 MODE 3 MODE 4 mcbsp3_dx gpio_158 mcbsp3_dr gpio_159 gpio_160 mcbsp3_fsx gpio_161 ...

  • Page 56

    ... MODE 4 hsusb2_data0 gpio_28 hsusb2_data1 gpio_29 gpio_1 gpio_30 gpio_2 gpio_3 gpio_4 gpio_5 gpio_6 gpio_7 gpio_8 gpio_10 gpio_11 gpio_31 Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com MODE 5 MODE 6 MODE 7 mm_fsusb2_rxrcv hw_dbg16 mm_fsusb2_txse hw_dbg17 0 safe_mode ...

  • Page 57

    ... GPMC Address bit 14multiplexed on gpmc_d13 gpmc_a15 GPMC Address bit15 multiplexed on gpmc_d14 gpmc_a16 GPMC Address bit16 multiplexed on gpmc_d15 gpmc_a17 GPMC Address bit17 multiplexed on gpmc_a1 Copyright © 2009–2011, Texas Instruments Incorporated TYPE[3] ZCN BALL[4] O E3/G5 O E2/G4 O E1/G3 O F7/G2 O F6/G1 O F4/H2 O ...

  • Page 58

    ... AA7 gpmc_a1/gpmc_d0 Y7 gpmc_a2/gpmc_d1 W7 gpmc_a3/gpmc_d2 AA9 gpmc_a4/gpmc_d3 Y8 gpmc_a5/gpmc_d4 AA8 gpmc_a6/gpmc_d5 AB8 gpmc_a7/gpmc_d6 W8 gpmc_a8/gpmc_d7 W10 gpmc_a9/gpmc_d8 AB9 gpmc_a10/gpmc_d9 AB10 gpmc_a11/gpmc_d10 W9 gpmc_a12/gpmc_d11 AA10 gpmc_a13/gpmc_d12 Y9 gpmc_a14/gpmc_d13 V10 gpmc_a15/gpmc_d14 V9 gpmc_a16/gpmc_d15 Y10 Y11 Y12 V12 AA11 W12 AA12 V11 AB13 Copyright © 2009–2011, Texas Instruments Incorporated [5] ...

  • Page 59

    ... SDRAM data bit 19 sdrc_d20 SDRAM data bit 20 sdrc_d21 SDRAM data bit 21 sdrc_d22 SDRAM data bit 22 sdrc_d23 SDRAM data bit 23 sdrc_d24 SDRAM data bit 24 sdrc_d25 SDRAM data bit 25 sdrc_d26 SDRAM data bit 26 Copyright © 2009–2011, Texas Instruments Incorporated TYPE[3] ZCN BALL[ ...

  • Page 60

    ... D10 O E10 E13 O A14 O A13 O B13 O D14 O C14 O E14 O B14 O C21 O B15 A19 A A18 B20 IO A20 IO B17 Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com [4] ZER BALL [4] Y4 AA2 AA3 AA4 AB2 AB3 Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 61

    ... CCDC data bit 15 (1) See Multiplexing Characteristics table for more information. Table 2-7. Video Interfaces - DSS Signals Description SIGNAL NAME[1] DESCRIPTION dss_pclk LCD Pixel Clock dss_hsync LCD Horizontal Synchronization dss_vsync LCD Vertical Synchronization Copyright © 2009–2011, Texas Instruments Incorporated [2] TYPE [3] ZCN BALL IO A17 ...

  • Page 62

    ... SUBSYSTEM PIN MULTIPLEXING B19 dss_acbias B21 dss_hsync A20 dss_data0 A19 dss_data1 A18 dss_data2 B18 dss_data3 A17 dss_data4 C18 dss_data5 D17 dss_data6 B16 dss_data7 B17 dss_data8 C17 dss_data9 C16 dss_data10 D16 dss_data11 D14 dss_data12 A16 dss_data13 Copyright © 2009–2011, Texas Instruments Incorporated [5] ...

  • Page 63

    ... Table 2-12. Serial Communication Interfaces - I2C Signals Description (I2C2) SIGNAL NAME [1] DESCRIPTION i2c2_scl I2C Master Serial clock. Output is open drain. i2c2_sda I2C Serial Bidirectional Data. Output is open drain. Copyright © 2009–2011, Texas Instruments Incorporated TYPE [3] ZCN BALL [4] IO W21 IO W22 AE23 O ...

  • Page 64

    ... AD17 IO AE19 [2] TYPE [3] ZCN BALL IO AE14 Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com [4] ZER BALL [4] W16 W17 [4] ZER BALL [4] C9 B11 D11 C10 C8 C11 E11 E19 F19 G22 F21 [4] ZER BALL [4] K22 Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 65

    ... Table 2-17. Serial Communication Interfaces – EMAC (RMII) Signals Description SIGNAL NAME [1] DESCRIPTION rmii_mdio_data Management data I/O rmii_mdio_clk Management data clock rmii_rxd0 EMAC receive data pin 0 rmii_rxd1 EMAC receive data pin 1 Copyright © 2009–2011, Texas Instruments Incorporated [2] TYPE [3] ZCN BALL AD15 IO AC15 IO AB15 O AD14 ...

  • Page 66

    ... Product Folder Link(s): AM3517 AM3505 www.ti.com [4] ZER BALL [4] T21 R22 T22 R20 R19 R21 [4] ZER BALL [4] C19,A20,E11 C21,A19 C20,B16,E22 C22,D17 A5,C4 B5,B4 C6,A4 D6,D4 W15,V14 W13AB16 AA13,A17,A6,AB15 Y13,C18,B6,A7 Y22,M21 Y21,M20 Y14,W21,L19 AA16,AA21,K20 [4] ZER BALL [ Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 67

    ... Differential receiver signal input (not used in 3-pin mode) mm_fsusb1_txse0 Single-ended zero. Used 4-pin VP_VM mode. mm_fsusb1_txdat USB data. Used 4-pin VP_VM mode. mm_fsusb1_txen_n Transmit enable HSUSB2 Copyright © 2009–2011, Texas Instruments Incorporated [2] TYPE [3] ZCN BALL A G24 IO AE13 IO AC13 IO A23 IO ...

  • Page 68

    ... AD20 IO AD18 IO AC18 IO AB18 Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com [4] ZER BALL [4] E22 E20 E18 D20 D19 D18 J21 H19 H20 H22 H21 J22 G21 G22 D22 D21 G20 F22 F20 Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 69

    ... DAT5, DAT6, and DAT7 signals case an external transceiver used mmc2_clkin MMC/SD input clock mmc2_dat0 MMC/SD Card Data bit 0 mmc2_dat1 MMC/SD Card Data bit 1 mmc2_dat2 MMC/SD Card Data bit 2 Copyright © 2009–2011, Texas Instruments Incorporated [2] TYPE [3] ZCN BALL IO AB19 IO Y18 IO AE19 ...

  • Page 70

    ... AC13,AE19 IO AD13,AD19 IO AE13,AA18 IO AD18 IO AD20 IO AE20 IO AB19 Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com [4] ZER BALL [4] K21 L18 L20 L21 M19 NA M20 J19,G22 J20,G21 E19,L18 L20,F21 L21,F19 M19,G19 G20 D21 D22 E21 Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 71

    ... Debug signal 4 hw_dbg5 Debug signal 5 hw_dbg6 Debug signal 6 hw_dbg7 Debug signal 7 hw_dbg8 Debug signal 8 hw_dbg9 Debug signal 9 hw_dbg10 Debug signal 10 hw_dbg11 Debug signal 11 hw_dbg12 Debug signal 12 Copyright © 2009–2011, Texas Instruments Incorporated [2] TYPE [3] ZCN BALL O AE18 O AD17 O AD18 O AC18 O AB18 O AA18 ...

  • Page 72

    ... AD22,AB20 O AB25,AE21 O AA23,AD21 O AA24,AC21 O AA25,AE22 [2] TYPE [3] ZCN BALL IO N4,E23,AE17 IO M4,M2,F20,AC16 IO M3,M1,F19,AB16 IO N5,E24,AA16 Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com [4] ZER BALL [4] E20 E18 D20 D19 D18 [4] ZER BALL [4] V11,C6,H19 Y12,AA11,A5,H20 V12,W12,B5,H22 AA12,D6,H21 Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 73

    ... General-purpose IO 39 gpio_40 General-purpose IO 40 gpio_41 General-purpose IO 41 gpio_42 General-purpose IO 42 gpio_43 General-purpose IO 43 gpio_44 General-purpose IO 44 gpio_45 General-purpose IO 45 gpio_46 General-purpose IO 46 gpio_47 General-purpose IO 47 Copyright © 2009–2011, Texas Instruments Incorporated [2] TYPE [3] ZCN BALL M24 AA1 IO AA2 IO AA3 IO ...

  • Page 74

    ... Y15 W14 AA16 Y14 V14 B22 B21 B20 B19 A20 A19 A18 B18 A17 C18 D17 B16 B17 C17 C16 D16 D14 A16 D15 B15 A15 A14 C13 C15 A13 B13 C14 B14 AB21 Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 75

    ... General-purpose IO 134 gpio_135 General-purpose IO 135 gpio_136 General-purpose IO 136 gpio_137 General-purpose IO 137 gpio_138 General-purpose IO 138 gpio_139 General-purpose IO 139 gpio_140 General-purpose IO 140 gpio_141 General-purpose IO 141 gpio_142 General-purpose IO 142 Copyright © 2009–2011, Texas Instruments Incorporated [2] TYPE [3] ZCN BALL IO AD1 IO AE2 IO AD3 IO AE3 I AD4 I AE4 ...

  • Page 76

    ... ZER BALL [ C22 C21 C19 C20 B11 D11 C10 C9 E11 C11 C8 W15 W13 AA13 Y13 R22 Y17 B9 K22 K19 J18 K18 J20 J19 J21 J22 H20 H22 H21 H19 Y16 W16 W17 E10 Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 77

    ... External DMA request 2 (system expansion). Level (active low) or edge (falling) selectable. sys_ndmareq3 External DMA request 3 (system expansion). Level (active low) or edge (falling) selectable. Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 TYPE [ ...

  • Page 78

    ... M12, M14, M16, M22, N7, N9, N11, N13, N15, N17, P6, P8, P10, P12, P14, P16, R5, R7, R9, R11, R13, R15, R17, T6, T8, T10, T12, T14, T16, T18, U5, U7, U9, U11, U13, U15, U17, V6, AB1, AB12, AB22 L17 J6 M17 K6 K17 F11 Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 79

    ... NAME[1] VDDSHV 1.8/3.3-V power supply. VDDS 1.8-V power supply. VDDSOSC 1.8-V oscillator power supply. VSSOSC Oscillator ground. Copyright © 2009–2011, Texas Instruments Incorporated BALL DESCRIPTION[2] (ZCN Pkg.) Y16, Y15, Y13, Y12, Y10, W16, W15, W13, W12,W10, W9, W6, V7, V6, U19, T20, T19, ...

  • Page 80

    ... VDDSHV = 3.3 V USB VBUS pin (usb0_vbus) USB 5V Tolerant IOs (usb0_dp, usb0_dm, usb0_id) (2) HBM (human body model) (3) CDM (charged device model) (4) Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com MIN MAX UNIT -0.5 1 ...

  • Page 81

    ... USB transceiver power supply VDDSHV 3.3-/1.8--V power supply VDDS 1.8-V power supply VDDSOSC 1.8-V oscillator power supply Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 DESCRIPTION AM3517 AM3505 Submit Documentation Feedback Product Folder Link(s): ...

  • Page 82

    ... Temperature Extended -40 Temperature < 90°C T 100K 105 °C T 100K J < 90°C T 100K J ( 105 °C T 50K J Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com Table 3-3. MAX UNIT 1.248 V 24.00 mVpp 1.89 V 50.00 mVpp 1 ...

  • Page 83

    ... The following diagram illustrates the power domains: vdds_dpll_mpu_usbhost BandGap LDO3 1.0 V/1.2 V BCK MEM vddshv vdds vdd_core vdds_dpll_per_core vdda_dac Dual Video DAC Copyright © 2009–2011, Texas Instruments Incorporated DLL/DCDL LDO MPU in 1.8 V out 1.2 V DPLL_MPU LDO in 1.8 V out 1.2 V Core SRAM 1 LDO 0 V/1.0 V/1.2 V ...

  • Page 84

    ... Low/Full speed 2.8 High speed 360 Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com NOM MAX UNIT V 0. VDDSHV 0.8 0.2 x VDDSOSC V 0.45 V 0.4 9 µA -70 270 286 20 µ 0.8 V (2) VDDA3P3V_ V USBPHY 440 mV Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 85

    ... Table 3-4. DC Electrical Characteristics (continued) PARAMETER V Low-level output voltage OL Copyright © 2009–2011, Texas Instruments Incorporated MIN Low/Full speed 0.0 High speed -10 Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 AM3517, AM3505 SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 ...

  • Page 86

    ... Cvddshv Cvdda3p3v_usbphy Cvdda1p8v_usbphy (1) 1 capacitor per balls 86 ELECTRICAL CHARACTERISTICS MIN TYP 50 100 100 100 100 100 100 100 100 100 100 100 Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com MAX UNIT 120 ...

  • Page 87

    ... Place the decoupling capacitor group balls; the total must be equal to the decoupling requirement. In case you interconnect powers, first insert the decoupling capacitor and then interconnect the powers. (2) The decoupling capacitor value depends on the board characteristics. Copyright © 2009–2011, Texas Instruments Incorporated Device vdds_sram_mpu ...

  • Page 88

    ... Note: In VDDSHV 1.8 V operation mode, VDDSHV can be grouped and powered up together with VDDS, VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU and VDDSOSC. 88 ELECTRICAL CHARACTERISTICS give an example of power-up . Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com sequence supported by Copyright © 2009–2011, Texas Instruments Incorporated the ...

  • Page 89

    ... VDD_CORE sys_nrespwron sys_32k sys_xtalin VDDS_DPLL_PER_CORE , VDDS_DPLL_MPU_USBHOST, VDDA_DAC, VDDA1P8V_USBPHY VDDA3P3V_USBPHY Copyright © 2009–2011, Texas Instruments Incorporated 3.3V 1.2V 1.8V 3.3V Figure 3-3. Power-up Sequence Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 AM3517, AM3505 SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 ...

  • Page 90

    ... Power off core domain (VDD_CORE) (c) Power off all PLL domains (VDDS_DPLL_MPU_USBHOST and VDDS_DPLL_PER_CORE) (d) Power off all SRAM LDOs (e) Power off all standard I/O domains (VDDS and VDDSHV) 90 ELECTRICAL CHARACTERISTICS Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com . ...

  • Page 91

    ... A crystal oscillator clock managed by sys_xtalin and sys_xtalout. In this case, the sys_clkreq is used as an input (GPIN). – A CMOS digital clock through the sys_xtalin pin. In this case, the sys_clkreq is used as an output to request the external system clock. Copyright © 2009–2011, Texas Instruments Incorporated Power IC Alternate Clock Source Selectable (54, 48 MHz or other [ MHz]) ...

  • Page 92

    ... CLOCK SPECIFICATIONS 0 Fixed 32.5 kHz 1 Divider /800 Sys_clk= 26 MHz 0 Latch 1 JTAG Overrides for DFT 1 Figure 4-2. 32-kHz Clock Generation Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com Sys_32k Sys_xtalin Sys_xtalout Sys_boot7 Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 93

    ... Alternate clock ( MHz, or other MHz) Table 4-2. 26Mhz sys_clk Input Clock Timing Requirements PARAMETER DESCRIPTION f(xtalin) Frequency, sys_xtalin tw(xtalin) Duty Cycle, sys_xtalin tj(xtalin) Jitter, sys_xtalin Copyright © 2009–2011, Texas Instruments Incorporated sys_xtalin sys_xtalout VSSOSC Crystal 26 MHz C1 C2 TYP MAX 26 50 ...

  • Page 94

    ... IH IL Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com MAX UNIT 5 ns MAX UNIT kHz 0. GΩ (1) TYP MAX UNIT 32 kHz +/-200 ppm MAX UNIT MHz 0. GΩ (1) (2) MAX UNIT MHz ppm Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 95

    ... NAME DESCRIPTION (1) f Frequency, sys_clkout2 (2) C Load capacitance L (1) The maximum frequency supported is core_clk/2 MHz. (2) The load capacitance is adapted to a frequency. Copyright © 2009–2011, Texas Instruments Incorporated MIN MIN 0. c(CLKOUT1) (1) (1) CO0 f(max) = 166 MHz Submit Documentation Feedback Product Folder Link(s): ...

  • Page 96

    ... With a load capacitance of 25 pF. sys_clkout2 Figure 4-5. sys_clkout2 System Output Clock 96 CLOCK SPECIFICATIONS MIN 0.40 * tc(CLKOUT2) (1) (1) CO0 Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com TYP MAX UNIT 166 MHz 0.60 * tc(CLKOUT2 ...

  • Page 97

    ... Fed with always-on system clock with independent gating control per DPLL • Analog part supplied through dedicated power supply (1.8 V) and an embedded LDO to get rid of 1-MHz noise • four independent output dividers for simultaneous generation of multiple clock frequencies Copyright © 2009–2011, Texas Instruments Incorporated Device Power Rail DPLL1 DPLL3 DPLL4 DPLL5 Figure 4-6 ...

  • Page 98

    ... CM. Its outputs to the DSS, PER, and EMU domains are propagated with always-on clock trees. 4.4.1.4 DPLL5 (Second peripherals DPLL) DPLL5 supplies the 120-MHz functional clock to the CM. 98 CLOCK SPECIFICATIONS Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com ...

  • Page 99

    ... The capacitors must be inserted between power and ground as close as possible. (2) This circuit is provided only as an example. (3) The filter must be located as close as possible to the device. (4) No filtering required if noise is below 10 mV Copyright © 2009–2011, Texas Instruments Incorporated for frequencies below 1 MHz. PP DLL ...

  • Page 100

    ... TVOUT TVOUT Video DAC 2 BUFFER BUFFER V_ref vssa_dac tv_vref C BG Figure 5-1. Video DAC Architecture Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com Figure 5-1 tv_vfb1 tv_out1 tv_vfb2 tv_out2 030-018 Table 5-2 Copyright © 2009–2011, Texas Instruments Incorporated and ...

  • Page 101

    ... Amplifier feedback node tv_vfb2 O Amplifier feedback node Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 DAC1 video output. An external resistor is connected between this node and tv_vfb1. The nominal value of ROUT1 is 1650 . Finally, note that this is the output node that drives the load (75 ). ...

  • Page 102

    ... Lasts less than 1 ns Measured MHz, f CLK OUT = 2 MHz sine wave, vdd = 1.3 V Lasts less than 30C, vdda = 1 30C, vdd = 1.3 V Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com MIN TYP MAX UNIT ...

  • Page 103

    ... The differential gain and phase value is for dc coupling. Note that there is degradation for the ac coupling. (3) The SNR value is for dc coupling. Note that there is a 6-dB degradation for ac coupling. (4) The PSSR value is for dc coupling. Note that there is a 10-dB degradation for ac coupling. Copyright © 2009–2011, Texas Instruments Incorporated = 1650 , unless otherwise noted) ...

  • Page 104

    ... Maximum Peak-to-Peak Noise on vdda_dac < 30 mVpp Decreases 20 dB/dec. Example MHz the maximum is 3 mVpp Table Maximum Supply Noise Density < Decreases 20 dB/dec. Example MHz the maximum noise density Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com % FSR ...

  • Page 105

    ... Table 5-7. Video DAC Recommended External Components Values OUT1/2 In order to limit the reference noise bandwidth and to suppress transients on V connect a large decoupling capacitor © Copyright © 2009–2011, Texas Instruments Incorporated is regulated by the reference amplifier, and is set by an internal OUTMAX OUT1/2 Recommended Value 100 1650 ) between the tv_vref and vssa_dac pins ...

  • Page 106

    ... Maximum pulse duration = typical pulse duration + maximum duty cycle error 106 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Cycle (or Period) Jitter n Figure 6-1. Cycle (or Period) Jitter Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com i 030-020 Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 107

    ... Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 Table 6-1. Timing Parameters LOWERCASE SUBSCRIPTS Unknown, changing, or dont care level TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 AM3517, AM3505 ...

  • Page 108

    ... Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com UNIT MAX 1 1.8V, 3.3V UNIT MIN MAX 2.021 ns 3.403 ns 3.782 ns 3.343 ns 1.8V, 3.3V UNIT MIN MAX 10 ns (2) (2) 0 (2) (2) 0 -500 500 ps Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 109

    ... B = ClkActivationTime * GPMC_FCLK (8) For single read (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst read (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst write (WrCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 MIN (3) , output clock ...

  • Page 110

    ... For burst read (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst write (WrCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK 110 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS MIN (9) G (10) D Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com 1.8V, 3.3V UNIT MAX ( ...

  • Page 111

    ... I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime - ClkActivationTime multiple of 3) • 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - multiple of 3) • 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - multiple of 3) (14 GPMC_FCLK period Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 MIN (11) H (12) ...

  • Page 112

    ... TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS MIN Read A (15) low Write A Read C Write C Read K Write K (11) H (19) M Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com 1.8V, 3.3V UNIT MAX (16) ns (16) ns (17) ns (17) ns (18) ns (18) ns (11 ...

  • Page 113

    ... In gpmc_ncsx equal gpmc_waitx equal Figure 6-2. GPMC/NOR Flash Synchronous Single Read (GpmcFCLKDivider = 0) Copyright © 2009–2011, Texas Instruments Incorporated Valid Address F6 F19 F19 F20 OUT OUT TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS ...

  • Page 114

    ... Figure 6-3. GPMC/NOR Flash Synchronous Burst Read 4x16-bit (GpmcFCLKDivider = 0) 114 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Valid Address F8 F8 F21 F23 OUT OUT Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com F10 F11 F13 F13 F12 F12 F22 F24 IN OUT 030-022 Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 115

    ... Valid Address F6 gpmc_nbe0_cle gpmc_nbe1 F6 gpmc_nadv_ale gpmc_nwe gpmc_d[15:0] gpmc_waitx gpmc_io_dir In gpmc_ncsx equal gpmc_waitx equal Figure 6-4. GPMC/NOR Flash Synchronous Burst Write (GpmcFCLKDivider = 0) Copyright © 2009–2011, Texas Instruments Incorporated F14 F14 D 0 OUT TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback ...

  • Page 116

    ... Figure 6-5. GPMC/Multiplexed NOR Flash Synchronous Burst Read 116 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS F2 F6 Valid F6 Valid F4 Address (MSB Address (LSB F10 F23 OUT OUT Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com F12 F13 F12 F11 F24 IN OUT 030-024 Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 117

    ... Maximum byte enable generation delay from internal functional clock (1) The internal parameters table must be used to calculate Data Access Time stored in the corresponding CS register bit field. (2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally. Copyright © 2009–2011, Texas Instruments Incorporated F1 F1 ...

  • Page 118

    ... B(2) + 2.0 ns – 0.2 C(3) + 2.0 ns – 0.2 J(9) + 2.0 ns – 0.2 J(9) + 2.0 ns – 0.2 K(10) + 2.0 ns – 0.2 L(11) + 2.0 ns – 0.2 L(11) + 2.0 ns – 0.2 M(14) + 2.0 ns G(7) ns Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 119

    ... RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses performed to Memory and multiplexed or non-multiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR behavior is automatically handled by GPMC controller. Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 MIN ...

  • Page 120

    ... TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS FA5 FA1 Valid Address FA0 Valid FA0 Valid FA3 FA12 FA4 FA13 FA14 OUT OUT Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com Data IN 0 Data IN 0 FA15 IN Timing(1) (2) (3) Copyright © 2009–2011, Texas Instruments Incorporated OUT 030-026 ...

  • Page 121

    ... From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bit field. (3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Copyright © 2009–2011, Texas Instruments Incorporated FA5 FA1 ...

  • Page 122

    ... TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS FA21 FA1 Add0 FA0 FA0 FA18 FA13 FA15 FA14 OUT Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com FA20 FA20 FA20 Add1 Add2 Add3 Add4 Timing(1) (2) (3) (4) Copyright © 2009–2011, Texas Instruments Incorporated D3 OUT 030-028 ...

  • Page 123

    ... FA12 gpmc_nadv_ale gpmc_nwe FA29 gpmc_d[15:0] gpmc_waitx gpmc_io_dir In gpmc_ncsx equal gpmc_waitx equal Figure 6-10. GPMC/NOR Flash – Asynchronous Write – Single Word Timing Copyright © 2009–2011, Texas Instruments Incorporated FA1 Valid Address FA0 FA0 FA3 FA27 FA25 Data OUT OUT ...

  • Page 124

    ... TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS FA1 FA5 Address (MSB) FA0 Valid FA0 Valid FA3 FA12 FA4 FA13 FA37 Address (LSB) FA15 FA14 Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com Data IN Data IN OUT IN Timing(1) (2) (3) Copyright © 2009–2011, Texas Instruments Incorporated 030-030 ...

  • Page 125

    ... Maximum device select generation delay from internal functional clock (1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field. (2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally. Copyright © 2009–2011, Texas Instruments Incorporated FA1 Address (MSB) ...

  • Page 126

    ... MAX (2) J GPMC_FCLK cycles 1.8V, 3.3V UNIT MAX 2.0 ns 2.0 ns A(1) ns B(2) + 2.0 ns C(3) + 2.0 ns D(4) + 2.0 ns E(5) + 2.0 ns F(6) + 2.0 ns G(7) + 2.0 ns C(3) + 2.0 ns F(6) + 2.0 ns H(8) ns I(9) + 2.0 ns K(10) ns L(11) ns M(12) + 2.0 ns Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 127

    ... GPMC_FCLK gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe gpmc_nwe gpmc_a[16:1]_d[15:0] In gpmc_ncsx equal Figure 6-14. GPMC/NAND Flash – Address Latch Cycle Timing Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 GNF1 GNF2 GNF0 GNF3 Command GNF1 GNF7 GNF9 ...

  • Page 128

    ... Figure 6-16. GPMC/NAND Flash – Data Write Cycle Timing 128 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS GNF12 GNF10 GNF14 GNF13 GNF1 GNF9 GNF0 GNF3 DATA Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com GNF15 DATA Timing(1) (2) (3) GNF6 GNF4 030-035 Copyright © 2009–2011, Texas Instruments Incorporated 030-034 ...

  • Page 129

    ... Supports prioritized refresh. – Programmable SDRAM refresh rate and backlog counter. – Programmable SDRAM timing parameters. – Supports only little endian. Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 16, 32, and 64-Bit CAS Latencies ...

  • Page 130

    ... DQ15 T UDM T UDQS T BA0 T BA1 A14 CAS T RAS CKE Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com LPDDR DQ0 DQ7 LDM LDQS DQ8 DQ15 UDM UDQS BA0 BA1 A0 A14 CS CAS RAS WE CKE CK CK Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 131

    ... Higher LPDDR speed grades operating at the specified speeds are supported due to inherent JEDEC LPDDR backwards compatibility. (2) 1 x16 LPDDR device is used for 16 bit LPDDR memory system. 1x32 or 2x16 LPDDR devices are used for a 32-bit LPDDR memory system. Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 T ...

  • Page 132

    ... Table DESCRIPTION Top Routing Mostly Horizontal Ground Power Internal Routing Ground Bottom Routing Mostly Vertical MIN TYP MAX UNIT NOTES Mils 4 Mils 18 Mils 8 Mils See Note See Note Ω Z Ω See Note Copyright © 2009–2011, Texas Instruments Incorporated 6-14. (1) (2) (3) ...

  • Page 133

    ... The region of the PCB used for the LPDDR circuitry must be isolated from other signals. The LPDDR keep out region is defined for this purpose and is shown in the placement and LPDDR routing. Additional clearances required for the keep out region are shown in Table 6-16. Copyright © 2009–2011, Texas Instruments Incorporated OFFSET ...

  • Page 134

    ... Product Folder Link(s): AM3517 AM3505 www.ti.com lists the signal net classes, and PIN NAMES sdrc_dqs0 sdrc_dqs1 sdrc_dqs2 sdrc_dqs3 PIN NAMES sdrc_ba, sdrc_a, sdrc_ncs0, sdrc_ncas, sdrc_nras, sdrc_nwe, sdrc_cke0 sdrc_d, sdrc_dm0 sdrc_d, sdrc_dm1 sdrc_d, sdrc_dm2 sdrc_d, sdrc_dm3 Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 135

    ... Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. (3) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes. Copyright © 2009–2011, Texas Instruments Incorporated Table 6-19. LPDDR Signal Terminations MIN ...

  • Page 136

    ... DQLM - 50 DQLM 4w 3w Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com (1) MAX UNIT NOTES 25 Mils See Note DQLM + 50 Mils See Note 100 Mils 100 Mils See Note See Note 100 Mils Copyright © 2009–2011, Texas Instruments Incorporated (2) (3) (2) (2) (4) , ...

  • Page 137

    ... Device count indicates number of dies package contains 2 dies, that is the maximum number of devices that can be connected. (3) 92 ball devices retained for legacy support. New designs should use 84 ball DDR2 devices. Electrically, the 92 and 84 ball DDR2 devices are the same. Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 Min ...

  • Page 138

    ... Table 6-23. Minimum PCB Stack Up Type Signal Top Routing Mostly Horizontal Plane Plane Signal Plane Signal Bottom Routing Mostly Vertical Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com Table 6-23. Description Ground Power Internal Routing Ground Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 139

    ... SDRC_nCLK T SDRC_ODT T VREFSSTL (A) 0.1µF DDR_PADREF See VREF Routing and Topology figure for information on capacitor placement. Figure 6-23. DDR2 Dual-Memory High Level Schematic Copyright © 2009–2011, Texas Instruments Incorporated Table 6-24. x16 DDR2 DQ0 DQ7 LDM LDQS LDQS# DQ8 DQ15 ...

  • Page 140

    ... BA0 BA1 BA2* A0 A14* CS1 CS2* CAS# RAS# WE# CKE CLK CLK# ODT* VREF (A) (A) 0.1 F µ 0.1 F µ Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com Vio1.8 0 µ Ω 0.1 F µ 1K Ω Copyright © 2009–2011, Texas Instruments Incorporated 1% 1% ...

  • Page 141

    ... The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For single-memory DDR2 systems, the second DDR2 device is omitted from the placement. Y Copyright © 2009–2011, Texas Instruments Incorporated Table 6-24. PCB Stack Up Specifications X A1 ...

  • Page 142

    ... Figure 6-26. DDR2 Keepout Region Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com Min Max Unit Notes (1) 1750 Mils See Notes (1) 1280 Mils See Notes (1) 650 Mils See Notes (3) See Note 4 w See Note Copyright © 2009–2011, Texas Instruments Incorporated (2) , ( (4) (5) ...

  • Page 143

    ... These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed (HS) bypass caps. (2) Only used on dual-memory systems Copyright © 2009–2011, Texas Instruments Incorporated Table 6-26. Bulk Bypass Capacitors TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS ...

  • Page 144

    ... Only used on dual-memory systems 144 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Table 6-27 contains the specification for the HS bypass capacitors Table 6-29 Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com lists the signal net classes, and ...

  • Page 145

    ... Only series termination is permitted, parallel or SST specifically disallowed. (2) Terminator values larger than typical only recommended to address EMI issues. (3) Termination value should be uniform across net class. Copyright © 2009–2011, Texas Instruments Incorporated Table 6-28. Clock Net Class Definitions Table 6-29. Signal Net Class Definitions ...

  • Page 146

    ... Microprocessor A1 Neck down to minimum in BGA escape regions is acceptable. Narrowing to accomodate via congestion for short distances is also acceptable. Best performance is obtained if the width of VREF is maximized Microprocessor A1 Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com ...

  • Page 147

    ... Figure 6-29 shows the topology and routing for the DQS and Dx net classes; the routes are point to point. Skew matching across bytes is not needed nor recommended. Figure 6-29. DQS and Dx Routing and Topology Copyright © 2009–2011, Texas Instruments Incorporated Min Typ (2) ...

  • Page 148

    ... Typ Max Unit Notes 2w 25 Mils See Note Mils See Notes (5) 50 100 Mils See Note 100 Mils See Note See Notes (6) See Notes (4) Table 6-33 contains the routing Copyright © 2009–2011, Texas Instruments Incorporated (4) (2) , (5) (5) (4) , (7) , ...

  • Page 149

    ... ODT should only be used with 1 chip select as shown in sdrc_odt should not be used. ODT signals should be tied off at the memory. Microprocessor Figure 6-31. ODT Connection Using One Chip select (sdrc_cs0) Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 Min 4w ...

  • Page 150

    ... An internal buffer block provides a high bandwidth path between the VPSS module and the external memory. The Cortex-A8 will process the image data based on application requirements. 150 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 ...

  • Page 151

    ... VDIN_CLK (Rising Edge) VDIN_D[xx] VF3, VF4, VF6 VDIN_HD, VDIN_VD, VDIN_FIELD VF5 VDIN_WEN Copyright © 2009–2011, Texas Instruments Incorporated Table 6-34. VPFE Timing Requirements PARAMETER PARAMETER VF1 VF7 VF2 Figure 6-32. VPFE0 Input Timings TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback ...

  • Page 152

    ... Figure 6-33. VPFE Output Timings VF18 VF20 PARAMETER Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com VF15, VF16, VF17 SPRS550-002 SPRS550-003 Figure 6-35). (1) 1.8V, 3.3V UNIT MIN MAX -4.215 4.215 ns -4.215 4.215 ns -4.215 4.215 ns -4.215 4.215 ns Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 153

    ... For more information, see the AM35x Technical Reference Manual (TRM) [literature number SPRUGR0]. (4) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the DISPC_DIVISOR register. Copyright © 2009–2011, Texas Instruments Incorporated PARAMETER (2) ...

  • Page 154

    ... For more information, see the AM35x Technical Reference Manual (TRM) [literature number SPRUGR0]. 154 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS DL5 DL4 DL3 Mode(1) (2) (3) (4) (5) Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com 030-062 ...

  • Page 155

    ... Cycle Time, mcbsp1_clkr/mcbspx_clkx (1) tW(CLKH) Typical pulse duration, mcbsp1_clkr / mcbspx_clkx high (1) In mcbspx, x identifies the McBSP number ( mcbsp1_clkr / mcbspx_clkx clock period. Copyright © 2009–2011, Texas Instruments Incorporated Table 6-38. McBSP Timing Conditions 1.8V, 3.3 V VALUE ( VDDSHV = 1.8V, 3.3V MIN 20.83 (2) 0 ...

  • Page 156

    ... Full Cycle 1.0 Slave Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com UNIT (2) 0.5*P ns 0.75 ns UNIT MAX ns ( VDDSHV=1.8V UNIT MIN MAX 5.0 ns 5.2 ns 4.0 ns 4.2 ns 5.8 ns 5.2 ns 1.5 ns 0.9 ns 5.2 ns 4.2 ns 0.5 ns 1.0 ns Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 157

    ... B5 tsu(FSV- Setup time, CLKAE) mcbsp1_fsr / mcbsp1_fsx valid before mcbsp1_clkr / mcbsp1_clkx active edge Copyright © 2009–2011, Texas Instruments Incorporated VDDSHV=3.3V MIN MAX 0.2 14.8 VDDSHV = 3.3V MIN MAX Full Cycle 5.2 Slave Half Cycle 4.2 ...

  • Page 158

    ... AM3517 AM3505 www.ti.com VDDSHV = 1.8V UNIT 0.5 ns 1.0 ns VDDSHV = 1.8V UNIT MIN MAX 0.7 14.8 ns VDDSHV = 1.8V UNIT MIN MAX 5.2 ns 4.2 ns 5.2 ns 1.0 ns VDDSHV = 1.8V UNIT MIN MAX 0.2 14.8 ns 0.6 14.8 ns 0.6 14.8 ns Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 159

    ... CLKXAE) mcbsp2_fsx valid before mcbsp2_clkx active edge B6 th(CLKXAE- Hold time, FSXV) mcbsp2_fsx valid after mcbsp2_clkx active edge Copyright © 2009–2011, Texas Instruments Incorporated VDDSHV = 3.3V MIN MAX Half Cycle 5.0 Master Half Cycle 5.2 Slave Full Cycle 4.2 Master Full Cycle 4 ...

  • Page 160

    ... VDDSHV = 1.8V UNIT MIN MAX 5.0 ns 5.2 ns 4.2 ns 4.2 ns 5.8 ns 5.2 ns 1.5 ns 0.9 ns 5.2 ns 4.2 ns 5.2 ns 1.0 ns VDDSHV = 1.8V UNIT MIN MAX 0.2 14.8 ns VDDSHV = 1.8V UNIT MIN MAX 5.2 ns 4.2 ns 5.2 ns 1.0 ns Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 161

    ... Table 6-58. McBSP3 (Set #1) Switching Characteristics - Rising Edge and Receive Mode No. PARAMETER B2 td(CLKXAE- Delay time, mcbsp3_clkx active FSXV) edge to mcbsp3_fsx valid Copyright © 2009–2011, Texas Instruments Incorporated VDDSHV = 3.3V MIN MAX 0.2 14.8 Master 0.6 14.8 Slave ...

  • Page 162

    ... VDDSHV = 1.8V UNIT MIN MAX 0.2 22.2 ns 0.6 22.2 ns 0.6 22.2 ns VDDSHV = 1.8V UNIT MIN MAX 7.5 ns 7.7 ns 5.6 ns 5.8 ns 8.3 ns 7.7 ns 1.5 ns 0.9 ns 7.7 ns 5.8 ns 7.7 ns 1.0 ns VDDSHV = 1.8V UNIT MIN MAX 0.2 22.2 ns Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 163

    ... CLKXAE) mcbsp3_fsx valid before mcbsp3_clkx active edge B6 th(CLKXAE- Hold time, FSV) mcbsp3_fsx valid after mcbsp3_clkx active edge Copyright © 2009–2011, Texas Instruments Incorporated VDDSHV = 3.3V MIN MAX Half Cycle 5.2 Slave Full Cycle 4.2 Slave Half Cycle 5.2 Slave Full Cycle 1 ...

  • Page 164

    ... MIN MAX 5.2 ns 4.2 ns 5.2 ns 1.0 ns VDDSHV = 1.8V UNIT MIN MAX 0.2 14.8 ns 0.6 14.8 ns 0.6 14.8 ns VDDSHV = 1.8V UNIT MIN MAX 5.0 ns 5.2 ns 4.2 ns 4.2 ns 5.8 ns 5.2 ns 1.5 ns 0.9 ns 5.2 ns 4.2 ns 5.2 ns 1.0 ns Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 165

    ... DRV) mcbsp4_dr valid after mcbsp4_clkx active edge B5 tsu(FSV- Setup time, CLKXAE) mcbsp4_fsx valid before mcbsp4_clkx active edge Copyright © 2009–2011, Texas Instruments Incorporated VDDSHV = 3.3V MIN MAX 0.2 14.8 VDDSHV = 3.3V MIN MAX Half Cycle 5.2 Slave Full Cycle 4.2 ...

  • Page 166

    ... UNIT MIN MAX 0.2 16.6 ns VDDSHV = 1.8V UNIT MIN MAX 7.7 ns 3.7 ns 1.0 ns 1.0 ns VDDSHV = 1.8V UNIT MIN MAX 0.2 16.6 ns 0.6 16.6 ns 0.6 17.3 ns VDDSHV = 1.8V UNIT MIN MAX 7.5 ns 7.7 ns 5.6 ns 5.8 ns Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 167

    ... Delay time, mcbsp4_clkx active FSXV) edge to mcbsp4_fsx valid B8 td(CLKXAE- Delay time, DXV) mcbsp4_clkx active edge to mcbsp4_dx valid Copyright © 2009–2011, Texas Instruments Incorporated VDDSHV = 3.3V Half Cycle 7.7 Master Half Cycle 5.2 Slave Full Cycle 1.5 Master Full Cycle ...

  • Page 168

    ... VDDSHV = 1.8V UNIT MIN MAX 0.7 14.8 ns VDDSHV = 1.8V UNIT MIN MAX 7.7 ns 5.8 ns 7.7 ns 1.0 ns VDDSHV = 1.8V UNIT MIN MAX 0.2 14.8 ns Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 169

    ... Setup time, CLKXAE) mcbsp5_fsx valid before mcbsp5_clkx active edge B6 th(CLKXAE- Hold time, FSXV) mcbsp5_fsx valid after mcbsp5_clkx active edge Copyright © 2009–2011, Texas Instruments Incorporated VDDSHV = 3.3V Master 0.6 14.8 Slave 0.6 14.8 VDDSHV = 3.3V MIN MAX Half Cycle 7.5 Master Half Cycle 7 ...

  • Page 170

    ... VDDSHV = 1.8V or 3.3V MIN 0 Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com VDDSHV = 1.8V UNIT MIN MAX 0.2 22.2 ns 0.6 22.2 ns 0.6 22.2 ns UNIT MAX 8 UNIT MAX 8. UNIT MAX 16 030-068 Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 171

    ... Figure 6-41. McBSP Falling Edge Receive Timing in Master Mode mcbspx_clkr B5 mcbspx_fsr mcbspx_dr Figure 6-42. McBSP Falling Edge Receive Timing in Slave Mode mcbspx_clkx mcbspx_fsx mcbspx_dx Figure 6-43. McBSP Falling Edge Transmit Timing in Master Mode Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 172

    ... SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 mcbspx_clkx B5 mcbspx_fsx mcbspx_dx Figure 6-44. McBSP Falling Edge Transmit Timing in Slave Mode 172 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com D6 D5 030-075 ...

  • Page 173

    ... The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all software configurable. (4) This timing applies to all configurations regardless of mcspix_clk polarity and which clock edges are used to drive output data and capture input data. Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 1.8 V MIN 41 ...

  • Page 174

    ... Bit n-1 Bit n-2 Bit n-3 MIN 2.56 2.93 Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com SS5 Bit 0 Bit 0 SS5 Bit 1 Bit 0 Bit 1 Bit 0 Mode(1) (2) (1) (2) 1.8 V 3.3 V UNIT MAX MIN MAX Copyright © 2009–2011, Texas Instruments Incorporated 030-076 ...

  • Page 175

    ... The input timing requirements are given by considering a rise time and a fall time of 4 ns. (2) In mcspi3_csn equal The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and mcspi3_somi is latched is all software configurable. Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 1.8 V MIN 20 ...

  • Page 176

    ... Modes 4.4 and 2 (7) Modes 4.4 and 3 (6) Modes 4.4 and 2 11.3 and 2 Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com (1) (2) (3) 3.3 V UNIT MIN MAX 41.67 ns -200 200 ps (5) (5) 0.45P ...

  • Page 177

    ... The active clock edge (rising or falling) on which mcspix_simo is driven and mcspi_somi data is latched is software configurable with the bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL. (2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL. (3) In mcspix equal mcspix_csn equal Copyright © 2009–2011, Texas Instruments Incorporated SM0 SM5 SM1 ...

  • Page 178

    ... Rise time, mmx_txse0 R(do) t Fall time, mmx_txse0 F(do) 178 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 1.8V, 3.3V 2.0 2.0 15.0 PARAMETER PARAMETER Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com UNIT 1.8V, 3.3V UNIT MIN MAX 14 ...

  • Page 179

    ... Delay time, mmx_txdat invalid before mmx_txen_n high d(DATV-TXENH) FSU18 t Delay time, mmx_txse0 invalid before mmx_txen_n high d(SE0V-TXENH) t Rise time, mmx_txen_n R(txen) Copyright © 2009–2011, Texas Instruments Incorporated Transmit FSU8 FSU7 FSU9 PARAMETER PARAMETER TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback ...

  • Page 180

    ... TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Mode (continued) PARAMETER Transmit FSU17 FSU16 FSU18 1.8V, 3.3V PARAMETER PARAMETER Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com 1.8V, 3.3V UNIT MIN MAX 4 ...

  • Page 181

    ... Setup time, hsusbx_dir valid before hsusbx_clk rising edge s(DIRV-CLKH) t Setup time, hsusbx_nxt valid before hsusbx_clk rising edge s(NXTV-CLKH) (1) In hsusbx equal Copyright © 2009–2011, Texas Instruments Incorporated Mode (continued) PARAMETER Transmit FSU24 FSU23 FSU25 . It allows high-speed transactions (up to 480 Mbit/s) on the USB ...

  • Page 182

    ... Data_OUT Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com (1) (continued) 1.8V, 3.3V UNIT MIN MAX 0.2 ns 0.2 ns 7.5 ns 0.2 ns (1) 1.8V, 3.3V UNIT MIN MAX 60 MHz 200 HSU3 HSU4 HSU5 HSU6 Data_IN Copyright © 2009–2011, Texas Instruments Incorporated 030-087 ...

  • Page 183

    ... For additional information related to USB OTG electrical parameters, please see the respective documents on the USB Implementers Forum web site (http://www.usb.org). Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS ...

  • Page 184

    ... HECCx_RX HECCx_TX Figure 6-51. HECC Transmit/Receive Timing 184 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS (see Figure 6-51) PARAMETER 2 4 Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com Figure 6-51) 1.8 V, 3.3 V UNIT MIN MAX ...

  • Page 185

    ... NO. 4 td(REFCLK-TXD) Output Delay Time, REF_CLK High to TXD Valid 5 td(REFCLK-TXEN) Output Delay Time, REF_CLK High to TXEN Valid Copyright © 2009–2011, Texas Instruments Incorporated PARAMETER Table 6-113. RMII Timing Conditions MIN 1 1 PARAMETER TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback ...

  • Page 186

    ... SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 REF_CLK 5 TXEN TXD[1:0] RXD[1:0] 8 CRS_DV RXER_IN 186 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Figure 6-52. RMII Timing Diagram Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com SPRS550-004 Copyright © 2009–2011, Texas Instruments Incorporated ...

  • Page 187

    ... MD_CLK MDIO_D (output) 6.6.9 Universal Asynchronous Receiver/Transmitter (UART) The AM3517/05 has four UARTs (one with Infrared Data Association [IrDA] and Consumer Infrared [CIR] modes). Copyright © 2009–2011, Texas Instruments Incorporated Figure 6-53 PARAMETER 1 4 Figure 6-53. MDIO Input Timing (see ...

  • Page 188

    ... TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS PARAMETER (baud_15) (baud_30) (baud_100 Start Bit Data Bits 5 4 Start Bit Data Bits Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com (1) 1.8V, 3.3V UNIT MIN MAX .96U 1.05U ns .96U 1.05U ...

  • Page 189

    ... Mbit/s (Double pulse) Table 6-120. UART IrDA—Rise and Fall Time—Receive 6.6.9.1.2 IrDA—Transmit Mode Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 Pulse duration ELECTRICAL PULSE DURATION MIN NOMINAL SIR 1.41 78 ...

  • Page 190

    ... Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com UNIT MAX 78.1 μs 19.5 μs μs 9.75 4.87 μs 3.25 μs 1.62 μs 419 ns 211 ns 128 ns 253 ns MAX UNIT s 68 MAX UNIT s 63 1.3 tBR Copyright © 2009–2011, Texas Instruments Incorporated 030-095 ...

  • Page 191

    ... Write bit-zero time LOW0 t Recovery time REC t Read bit strobe time LOWR tRTSL 1-WIRE Copyright © 2009–2011, Texas Instruments Incorporated tCYCH tHW0 Figure 6-58. HDQ Read Bit Timing (Data) tCYCD tDW0 tRSPS 6 7_(MSB) assume testing over the recommended operating conditions (see ...

  • Page 192

    ... Figure 6-62. 1-Wire Read Bit Timing (Data) 1-WIRE tLOW1 Figure 6-63. 1-Wire Write Bit Timing (Command/Address or Data) 192 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS tSLOT_and_ tREC tRDV_and_ tREL tSLOT_and_tREC tLOW0 Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com 030-100 030-101 ...

  • Page 193

    ... After this time, the first clock is generated. Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 2 C device is recognized by a unique address and can ...

  • Page 194

    ... SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 START i2cX_sda I6 i2cX_scl 194 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS START REPEAT Figure 6-64 Standard/Fast Mode Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com START STOP Copyright © 2009–2011, Texas Instruments Incorporated 030-093 ...

  • Page 195

    ... HS-mode master devices generate a serial clock signal with a high-to-low ratio (2) In i2cX equal (3) After this time, the first clock is generated. Table 6-128. Correspondence Standard vs. TI Timing References Copyright © 2009–2011, Texas Instruments Incorporated 2 C High-Speed Mode Timings PARAMETER (4) condition or a repeated START High-Speed Mode(1) (2) (3) AM3517/05 ...

  • Page 196

    ... For more information, see the AM35x Technical Reference Manual (TRM) [literature number SPRUGR0]. 196 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS MIN PARAMETER Table 6-131. Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com : 1.8V, 3.3V ...

  • Page 197

    ... The jitter probability density can be approximated by a Gaussian function. (3) The X parameter is defined as shown below. ( output clk period in ns. (5) The Y parameter is defined as shown below. CLKD 1 or Even Odd Copyright © 2009–2011, Texas Instruments Incorporated SPRS550C – OCTOBER 2009 – REVISED MARCH 2011 PARAMETER PARAMETER Table 6-132. X Parameter X 0.5 ...

  • Page 198

    ... V MIN 2.13 3.47 2.13 3.47 2.88 2.90 2.88 2.90 3.38 2.83 3.38 2.83 Table 6-136. Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com UNIT MAX (1) (2) (3) (4) 3.3V UNIT MAX MIN MAX 2 ...

  • Page 199

    ... The X parameter is defined as shown below. ( output clk period in ns. (5) The Y parameter is defined as shown below. CLKD 1 or Even Odd CLKD 1 or Even Odd Copyright © 2009–2011, Texas Instruments Incorporated PARAMETER Table 6-137. X Parameter X 0.5 (trunc[CLKD/2]+1)/CLKD Table 6-138. Y Parameter Y 0.5 (trunc[CLKD/2])/CLKD ...

  • Page 200

    ... Input signal rise time r t Input signal fall time f Output Conditions C Output load capacitance LOAD 200 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 1.8-V,3.3-V MIN 0.19 0.19 Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 www.ti.com UNIT MAX ...