AM3715CBC

Manufacturer Part NumberAM3715CBC
DescriptionIC ARM MICROPROCESSOR 515FCBGA
ManufacturerTexas Instruments
SeriesSitara ARM®, Cortex™A8, ARM9
AM3715CBC datasheet
 


Specifications of AM3715CBC

Processor TypeARM MicroprocessorSpeed800MHz
Voltage1.8VMounting TypeSurface Mount
Package / Case515-VFBGA, FCBGALead Free Status / RoHS StatusLead free / RoHS Compliant
Features-  
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1 AM3715, AM3703 Sitara ARM Microprocessors
1.1
Features
123456
• AM3715/03 Sitara ARM Microprocessors:
– Compatible with OMAP™ 3 Architecture
®
– Sitara™ ARM
Microprocessor (MPU)
Subsystem
Up to 1-GHz Sitara™ ARM
Core
Also supports 300, 600, and 800-MHz
operation
NEON™ SIMD Coprocessor
– POWERVR SGX™ Graphics Accelerator
(AM3715 only)
Tile Based Architecture Delivering up to
20 MPoly/sec
Universal Scalable Shader Engine:
Multi-threaded Engine Incorporating Pixel
and Vertex Shader Functionality
Industry Standard API Support:
OpenGLES 1.1 and 2.0, OpenVG1.0
Fine Grained Task Switching, Load
Balancing, and Power Management
Programmable High Quality Image
Anti-Aliasing
– External Memory Interfaces:
SDRAM Controller (SDRC)
– 16, 32-bit Memory Controller With
1G-Byte Total Address Space
– Interfaces to Low-Power SDRAM
– SDRAM Memory Scheduler (SMS) and
Rotation Engine
General Purpose Memory Controller
(GPMC)
– 16-bit Wide Multiplexed Address/Data
Bus
– Up to 8 Chip Select Pins With
128M-Byte Address Space per Chip
Select Pin
– Glueless Interface to NOR Flash,
NAND Flash (With ECC Hamming
Code Calculation), SRAM and
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
POWERVR SGX is a trademark of Imagination Technologies Ltd.
2
OMAP, Sitara are trademarks of Texas Instruments.
3
Cortex, NEON are trademarks of ARM Limited.
4
ARM is a registered trademark of ARM Ltd.
5
All other trademarks are the property of their respective owners.
6
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
AM3715, AM3703
Sitara ARM Microprocessors
Check for Samples: AM3715,
AM3703
– Flexible Asynchronous Protocol
– Nonmultiplexed Address/Data Mode
®
Cortex™-A8
– 1.8-V I/O and 3.0-V (MMC1 only),
0.9-V to 1.2-V Adaptive Processor Core
Voltage
0.9-V to 1.1-V Adaptive Core Logic Voltage
Note: These are default Operating
Performance Point (OPP) voltages and could
be optimized to lower values using
SmartReflex AVS.
– Commercial, Industrial, and Extended
Temperature Grades
– Serial Communication
5 Multichannel Buffered Serial Ports
(McBSPs)
– 512 Byte Transmit/Receive Buffer
– 5K-Byte Transmit/Receive Buffer
– SIDETONE Core Support (McBSP2 and
– Direct Interface to I2S and PCM Device
– 128 Channel Transmit/Receive Mode
Four Master/Slave Multichannel Serial
Port Interface (McSPI) Ports
High-Speed/Full-Speed/Low-Speed USB
OTG Subsystem (12-/8-Pin ULPI Interface)
High-Speed/Full-Speed/Low-Speed
Multiport USB Host Subsystem
– 12-/8-Pin ULPI Interface or 6-/4-/3-Pin
One HDQ/1-Wire Interface
Four UARTs (One with Infrared Data
Association [IrDA] and Consumer Infrared
AM3715, AM3703
SPRS616F – JUNE 2010 – REVISED APRIL 2011
Pseudo-SRAM
Control for Interface to Custom Logic
(FPGA, CPLD, ASICs, etc.)
(Limited 2K-Byte Address Space)
(McBSP1/3/4/5)
(McBSP2)
3 Only) For Filter, Gain, and Mix
Operations
and T Buses
Serial Interface
Copyright © 2010–2011, Texas Instruments Incorporated

AM3715CBC Summary of contents

  • Page 1

    ... Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. POWERVR SGX is a trademark of Imagination Technologies Ltd. 2 OMAP, Sitara are trademarks of Texas Instruments. 3 Cortex, NEON are trademarks of ARM Limited. 4 ARM is a registered trademark of ARM Ltd ...

  • Page 2

    ... Ball Pitch (Top), .4mm Ball Pitch (Bottom) – 515-pin s-PBGA package (CBC Suffix), .65mm Ball Pitch (Top), .5mm Ball Pitch (Bottom) – 423-pin s-PBGA package (CUS Suffix), .65mm Ball Pitch Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com ...

  • Page 3

    ... The clock specifications: input and output clocks, DPLL and DLL • A description of thermal characteristics, device nomenclature, and mechanical data about the available packaging Copyright © 2010–2011, Texas Instruments Incorporated AM3715, AM3703 Sitara ARM Microprocessors Submit Documentation Feedback Product Folder Link(s): ...

  • Page 4

    ... Product Folder Link(s): AM3715 AM3703 www.ti.com CVBS or S-Video Camera (Parallel) Amp Parallel TV Camera ISP HS USB Image Host Capture HS Hardware USB Image OTG Pipeline ® Interconnect System Controls PRCM 2xSmartReflex Control Module External Peripherals Interfaces Emulation Copyright © 2010–2011, Texas Instruments Incorporated TM ...

  • Page 5

    ... Clock Specifications • • Added: • Copyright © 2010–2011, Texas Instruments Incorporated Revision History Revision History Table 2-1. Ball Characteristics (CBP Pkg.). Removed restriction note from GPIO_16. Table 2-2. Ball Characteristics (CBC Pkg.). Removed restriction note from GPIO_16. Table 2-3. Ball Characteristics (CUS Pkg.). Removed restriction note from GPIO_16. ...

  • Page 6

    ... Table 2-25 indicate the signal names and ball grid numbers for Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com 030-001 Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 7

    ... Figure 2-2. AM3715/03 Microprocessor CBP s-PBGA-N515 Package (Top View) Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 AM3715, AM3703 SPRS616F – JUNE 2010 – REVISED APRIL 2011 030-002 TERMINAL DESCRIPTION 7 ...

  • Page 8

    ... AM3715, AM3703 SPRS616F – JUNE 2010 – REVISED APRIL 2011 Figure 2-3. AM3715/03 Microprocessor CBC s-PBGA-515 Package (Bottom View) 8 TERMINAL DESCRIPTION Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com ...

  • Page 9

    ... Figure 2-4. AM3715/03 Microprocessor CBC s-PBGA-515 Package (Top View) Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 AM3715, AM3703 SPRS616F – JUNE 2010 – REVISED APRIL 2011 TERMINAL DESCRIPTION 9 ...

  • Page 10

    ... B, C, and D). Note: A pin with an "NC" designator indicates No Connection. For proper device operation, these pins must be left unconnected. 10 TERMINAL DESCRIPTION Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 11

    ... M _m1 _m2 pop_u1 pop_l2 gpmc_a7 gpmc_a1 N _n1 _n2 gpmc_d10 gpmc_d3 P vss vss A. Top Views are provided to assist in hardware debugging efforts. Figure 2-6. CBP Pin Map [Quadrant A - Top View] Copyright © 2010–2011, Texas Instruments Incorporated vdds_mem vdds_mem vss vss vdd_core ...

  • Page 12

    ... Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 13

    ... AH _dat5 _dat1 _dat0 _ah2 _ah1 Figure 2-8. CBP Pin Map [Quadrant C - Top View] Copyright © 2010–2011, Texas Instruments Incorporated vdd_mpu gpmc_ncs5 _iva vdd_mpu gpmc_ncs4 _iva gpmc_ncs3 vss gpmc_ncs2 vss vdd_mpu uart1_cts _iva vdd_mpu uart1_rx _iva ...

  • Page 14

    ... NC _ae28 pop_h23 sys sys_clkreq sys_nirq pop_aa22 _af28 _af27 _nreswarm pop_ab23 dss_data4 sys_clkout1 sys_boot1 vdds _ag28 sys pop_ac23 pop_ac22 dss_data5 sys_boot0 _nrespwron _ah27 _ah28 Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 15

    ... M _nwe _d15 _dat5 gpmc gpmc mcbsp3 N vss _clk _noe _dr A. Top Views are provided to assist in hardware debugging efforts. Figure 2-10. CBC Pin Map [Quadrant A - Top View] Copyright © 2010–2011, Texas Instruments Incorporated vss NC vss NC gpmc_ gpmc_ ncs6 ncs3 ...

  • Page 16

    ... NC rx_ data7 data8 irrx dss_ hdq_sio i2c1_sda i2c1_scl data9 pop_ dss_ NC vss h21_k26 hsync dss_ dss_ vdds vss data16 data17 dss_ dss_ dss_ NC data18 vsync data19 vdds_ dss_ cam_d8 cam_d9 mmc1 data21 Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 17

    ... AE NC _ae2 pop_y2 _af4 Figure 2-12. CBC Pin Map [Quadrant C - Top View] Copyright © 2010–2011, Texas Instruments Incorporated mcspi1 mcspi1 mcspi1 _somi _simo _clk mcspi1 mcspi1 mcspi1 _cs0 _cs1 _cs2 mcspi1 mmc2 vdd_ vdd_ _cs3 _dat1 ...

  • Page 18

    ... Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com vdds_x cam_d7 NC cam_d6 vss vdds cvideo2 pop_ NC ...

  • Page 19

    ... M _d1 _d2 _d4 _cs1 A. Top Views are provided to assist in hardware debugging efforts. Figure 2-14. CUS Pin Map [Quadrant A - Top View] Copyright © 2010–2011, Texas Instruments Incorporated sdrc sdrc sdrc _dqs0 _dm2 _dqs2 sdrc sdrc_d3 ...

  • Page 20

    ... F vsync data9 dss_ dss_ dss_ cam_d11 G pclk data17 data18 dss_ cam_fld H data19 dss_ dss_ cam_d8 J acbias data16 dss_ i2c1_sda cam_d9 cam_d7 K data21 mmc1_ cam_d6 L cmd mmc1_ mmc1_ mmc1_ M dat1 dat0 clk Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 21

    ... AB _dat4 _dat0 uart1_ etk_clk etk_d10 etk_d8 AC cts etk_d5 etk_ctl Figure 2-16. CUS Pin Map [Quadrant C - Top View] Copyright © 2010–2011, Texas Instruments Incorporated mcspi2 vdd_mpu vdd_mpu vdd_mpu _clk _iva _iva _iva vss mcbsp1 vdd_mpu vdd_mpu vdd_mpu _cs3 _iva _iva _iva ...

  • Page 22

    ... W _data6 _data4 data23 data14 cvideo2 cvideo1 dss_ Y data13 _vfb _rset cvideo2 AA _out cvideo1 cvideo1 dss_ AB data12 _vfb _out dss_ dss_ dss_ jtag_ AC data5 data10 data11 emu0 sys_off dss_ jtag_ AD _mode data4 emu1 Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 23

    ... POWER: The voltage supply that powers the terminal’s I/O buffers. 9. HYS: Indicates if the input buffer is with hysteresis. 10. BUFFER STRENGTH: Drive strength of the associated output buffer. Copyright © 2010–2011, Texas Instruments Incorporated describe the terminal characteristics and the signals multiplexed on each pin Section 2 ...

  • Page 24

    ... PU/ PD LVCMOS (12) Yes 4 PU/ PD LVCMOS (12) Yes 4 PU/ PD LVCMOS (12) Yes 4 PU/ PD LVCMOS (12) Yes 4 PU/ PD LVCMOS (12) Yes 4 PU/ PD LVCMOS (12) Yes 4 PU/ PD LVCMOS (12) Yes 4 PU/ PD LVCMOS (12) Yes 4 PU/ PD LVCMOS (12) Yes 4 PU/ PD LVCMOS (12) Yes 4 PU/ PD LVCMOS (12 LVCMOS (12 LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 25

    ... K4 AB16 gpmc_a4 0 gpio_37 4 safe_mode 7 T3 AC17 gpmc_a5 0 gpio_38 4 safe_mode 7 R3 AB17 gpmc_a6 0 gpio_39 4 safe_mode 7 Copyright © 2010–2011, Texas Instruments Incorporated (3) BALL BALL RESET RESET TYPE [4] RESET REL. MODE POWER REL. STATE [5] [7] STATE [ vdds_mem vdds_mem vdds_mem ...

  • Page 26

    ... Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS LVCMOS Yes 8 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 27

    ... H1 AB10 gpmc_nwp 0 gpio_62 4 safe_mode 7 M8 AB12 gpmc_wait0 0 L8 AC10 gpmc_wait1 0 gpio_63 4 safe_mode gpmc_wait2 0 uart4_tx 2 gpio_64 4 safe_mode 7 Copyright © 2010–2011, Texas Instruments Incorporated (3) BALL BALL RESET RESET TYPE [4] RESET REL. MODE POWER REL. STATE [5] [7] STATE [ vdds_mem vdds_mem vdds_mem ...

  • Page 28

    ... PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS 8 8 Yes 8 PU/ PD LVCMOS 8 8 Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 29

    ... H25 NA dss_data19 0 mcspi3_simo 2 dss_data1 3 gpio_89 4 safe_mode 7 E28 NA dss_data20 0 mcspi3_somi 2 dss_data2 3 gpio_90 4 safe_mode 7 J26 NA dss_data21 0 mcspi3_cs0 2 dss_data3 3 gpio_91 4 safe_mode 7 Copyright © 2010–2011, Texas Instruments Incorporated (3) BALL BALL RESET RESET TYPE [4] RESET REL. MODE POWER REL. STATE [5] [7] STATE [ vdds vdds vdds ...

  • Page 30

    ... DAC Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes NA PU/PD LVCMOS Yes NA PU/PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 31

    ... P21 NA mcbsp2_fsx 0 gpio_116 4 safe_mode 7 N21 NA mcbsp2_clkx 0 gpio_117 4 safe_mode 7 R21 NA mcbsp2_dr 0 gpio_118 4 safe_mode 7 M21 NA mcbsp2_dx 0 gpio_119 4 safe_mode 7 Copyright © 2010–2011, Texas Instruments Incorporated (3) BALL BALL RESET RESET TYPE [4] RESET REL. MODE POWER REL. STATE [5] [7] STATE [ vdds vdds vdds I I ...

  • Page 32

    ... LVCMOS (5) Yes 1 PU/ PD LVCMOS (5) Yes 1 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS (5) Yes 1 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 33

    ... AB26 NA uart2_cts 0 mcbsp3_dx 1 gpt_9_pwm_evt 2 gpio_144 4 safe_mode 7 AB25 NA uart2_rts 0 mcbsp3_dr 1 gpt_10_pwm_evt 2 gpio_145 4 safe_mode 7 AA25 NA uart2_tx 0 mcbsp3_clkx 1 gpt_11_pwm_evt 2 gpio_146 4 safe_mode 7 Copyright © 2010–2011, Texas Instruments Incorporated (3) BALL BALL RESET RESET TYPE [4] RESET REL. MODE POWER REL. STATE [5] [7] STATE [ vdds vdds ...

  • Page 34

    ... LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 35

    ... U28 NA hsusb0_data1 0 uart3_rx_irrx 2 gpio_130 4 uart2_rx 5 safe_mode 7 U27 NA hsusb0_data2 0 uart3_rts_sd 2 gpio_131 4 uart2_rts 5 safe_mode 7 U26 NA hsusb0_data3 0 uart3_cts_rctx 2 Copyright © 2010–2011, Texas Instruments Incorporated (3) BALL BALL RESET RESET TYPE [4] RESET REL. MODE POWER REL. STATE [5] [7] STATE [ vdds vdds ...

  • Page 36

    ... Yes 3 PU/ PD Open Drain 4 (6) (8) Yes 3 PU/ PD Open Drain 4 (6)(7) Yes 3 PU/ PD Open Drain 4 (6)(7) Yes 3 PU/ PD Open Drain 4 Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 37

    ... AE17 NA sys_xtalin 0 AF17 NA sys_xtalout 0 AF25 NA sys_clkreq 0 gpio_1 4 safe_mode 7 AF26 NA sys_nirq 0 gpio_0 4 safe_mode 7 AH25 NA sys_nrespwron 0 AF24 NA sys_nreswarm 0 gpio_30 4 Copyright © 2010–2011, Texas Instruments Incorporated (3) BALL BALL RESET RESET TYPE [4] RESET REL. MODE POWER REL. STATE [5] [7] STATE [ vdds vdds vdds ...

  • Page 38

    ... LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes NA PU/ PD LVCMOS Yes NA PU/ PD LVCMOS NA 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes NA PU/ PD LVCMOS NA 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 39

    ... AH9 NA etk_d5 0 mcbsp5_fsx 1 mmc3_dat1 2 hsusb1_ data5 3 gpio_19 4 hw_dbg7 7 AF13 NA etk_d6 0 mcbsp5_dx 1 mmc3_dat2 2 hsusb1_ data6 3 gpio_20 4 hw_dbg8 7 AH14 NA etk_d7 0 mcspi3_cs1 1 Copyright © 2010–2011, Texas Instruments Incorporated (3) BALL BALL RESET RESET TYPE [4] RESET REL. MODE POWER REL. STATE [5] [7] STATE [ vdds vdds ...

  • Page 40

    ... BUFFER PULLUP IO CELL [8] HYS [9] STRENGTH /DOWN [12] (mA) [10] TYPE [11] Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 41

    ... F25, F26 W16 NA vdds_sram 0 K15 NA vdda_dplls_dll 0 AA16 NA vdda_dpll_per 0 AA14 NA vdda_wkup_ 0 bg_bb K25 NA vdds_mmc1 0 V25 NA vdda_dac 0 Y26 NA vssa_dac 0 Copyright © 2010–2011, Texas Instruments Incorporated (3) BALL BALL RESET RESET TYPE [4] RESET REL. MODE POWER REL. STATE [5] [7] STATE [6] PWR - - - - PWR - - - - PWR - - - ...

  • Page 42

    ... TERMINAL DESCRIPTION (3) BALL BALL RESET RESET TYPE [4] RESET REL. MODE POWER REL. STATE [5] [7] STATE [6] GND - - - - PWR - - - - - - - - - Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com (continued) BUFFER PULLUP IO CELL [8] HYS [9] STRENGTH /DOWN [12] (mA) [10] TYPE [11 Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 43

    ... Technical Reference Manual (literature number SPRUGN4). (12) The drive strength of these IOs is set according to the programmable load range per default pF. For a full description of the drive strength programming, see the System Control Module chapter of the AM/DM37x Multimedia Device Technical Copyright © 2010–2011, Texas Instruments Incorporated (3) BALL ...

  • Page 44

    ... PU/ PD LVCMOS ( PU/ PD LVCMOS ( PU/ PD LVCMOS ( PU/ PD LVCMOS ( PU/ PD LVCMOS (1) Yes 4 PU/ PD LVCMOS (1) Yes 4 PU/ PD LVCMOS (1) Yes 4 PU/ PD LVCMOS (1) Yes 4 PU/ PD LVCMOS (1) Yes 4 PU/ PD LVCMOS (1) Yes 4 PU/ PD LVCMOS (1) Yes 4 PU/ PD LVCMOS (1) Yes 4 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 45

    ... AE22 NA dss_data1 0 uart1_rts 2 gpio_71 4 safe_mode 7 AE23 NA dss_data2 0 gpio_72 4 safe_mode 7 AE24 NA dss_data3 0 gpio_73 4 safe_mode 7 AD23 NA dss_data4 0 uart3_rx_irrx 2 Copyright © 2010–2011, Texas Instruments Incorporated (5) TYPE [4] BALL BALL RESET RESET POWER RESET REL. STATE REL. MODE STATE [5] [6] [ vdds vdds vdds vdds ...

  • Page 46

    ... LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 47

    ... U1 P1 gpmc_d12 0 gpio_48 4 safe_mode gpmc_d13 0 gpio_49 4 safe_mode gpmc_d14 0 gpio_50 4 safe_mode gpmc_d15 0 gpio_51 4 safe_mode 7 AD10 AA9 gpmc_nadv_ale 0 Copyright © 2010–2011, Texas Instruments Incorporated (5) TYPE [4] BALL BALL RESET RESET POWER RESET REL. STATE REL. MODE STATE [5] [6] [ vdds vdds vdds vdds ...

  • Page 48

    ... PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS LVCMOS LVCMOS Yes 8 PU/ PD LVCMOS Yes NA PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 49

    ... U20 NA hsusb0_stp 0 gpio_121 4 safe_mode 7 U15 NA jtag_ntrst 0 W13 NA jtag_rtck 0 V14 NA jtag_tck 0 U16 NA jtag_tdi 0 Y13 NA jtag_tdo 0 V15 NA jtag_tms_tmsc 0 Copyright © 2010–2011, Texas Instruments Incorporated (5) TYPE [4] BALL BALL RESET RESET POWER RESET REL. STATE REL. MODE STATE [5] [6] [ vdds vdds ...

  • Page 50

    ... Yes 3 PU/ PD LVCMOS Open Drain 4 4 (9)(11) Yes 3 PU/ PD LVCMOS Open Drain 4 4 (9)(11) Yes 3 PU/ PD LVCMOS Open Drain 4 4 (9)(11) Yes 3 PU/ PD LVCMOS Open Drain 4 4 Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 51

    ... R9 NA mcspi1_cs2 0 mmc3_clk 3 gpio_176 4 safe_mode mcspi1_simo 0 mmc2_dat5 1 gpio_172 4 safe_mode mcspi1_somi 0 mmc2_dat6 1 gpio_173 4 safe_mode mcspi2_clk 0 hsusb2_data7 3 gpio_178 4 safe_mode 7 Copyright © 2010–2011, Texas Instruments Incorporated (5) TYPE [4] BALL BALL RESET RESET POWER RESET REL. STATE REL. MODE STATE [5] [6] [ vdds vdds vdds ...

  • Page 52

    ... LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 53

    ... AD15 NA i2c4_scl 0 sys_nvmode1 1 safe_mode 7 W16 NA i2c4_sda 0 sys_nvmode2 1 safe_mode sys_boot0 0 dss_data18 3 gpio_2 4 safe_mode sys_boot1 0 dss_data19 3 gpio_3 4 safe_mode sys_boot2 0 gpio_4 4 Copyright © 2010–2011, Texas Instruments Incorporated (5) TYPE [4] BALL BALL RESET RESET POWER RESET REL. STATE REL. MODE STATE [5] [6] [ vdds vdds vdds IO ...

  • Page 54

    ... NA No LVCMOS Yes 4 PU/ PD LVCMOS Open Drain Yes 4 PU/ PD LVCMOS Yes NA NA LVCMOS Analog Analog 10-bit DAC 10-bit DAC 10-bit DAC 10-bit DAC 10-bit DAC Yes NA PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 55

    ... P26 NA cam_d7 0 gpio_106 4 safe_mode 7 N25 NA cam_d8 0 gpio_107 4 safe_mode 7 N26 NA cam_d9 0 gpio_108 4 safe_mode 7 D23 NA cam_vs 0 gpio_95 4 hw_dbg1 5 safe_mode 7 Copyright © 2010–2011, Texas Instruments Incorporated (5) TYPE [4] BALL BALL RESET RESET POWER RESET REL. STATE REL. MODE STATE [5] [6] [ vdds vdds vdds IO ...

  • Page 56

    ... LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 57

    ... AD4 NA etk_d1 0 mcspi3_somi 1 hsusb1_data1 3 gpio_15 4 mm1_txse0 5 hw_dbg3 7 AD3 NA etk_d2 0 mcspi3_cs0 1 hsusb1_data2 3 gpio_16 4 mm1_txdat 5 hw_dbg4 7 AA3 NA etk_d3 0 mcspi3_clk 1 mmc3_dat3 2 Copyright © 2010–2011, Texas Instruments Incorporated (5) TYPE [4] BALL BALL RESET RESET POWER RESET REL. STATE REL. MODE STATE [5] [6] [ vdds vdds vdds ...

  • Page 58

    ... STRENGTH /DOWN [12] (mA) [10] TYPE [11] Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 59

    ... U4 NA mcbsp4_dr 0 gpio_153 4 mm3_rxrcv 6 safe_mode mcbsp4_dx 0 gpio_154 4 mm3_txdat 6 safe_mode mcbsp4_fsx 0 gpio_155 4 mm3_txen_n 6 safe_mode mmc2_dat5 0 mmc2_dir_dat1 1 cam_global_reset 2 mmc3_dat1 3 Copyright © 2010–2011, Texas Instruments Incorporated (5) TYPE [4] BALL BALL RESET RESET POWER RESET REL. STATE REL. MODE STATE [5] [6] [ vdds vdds vdds ...

  • Page 60

    ... PWR - - - - PWR - - - - PWR - - - - PWR - - - - GND - - - - Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com (continued) [8] HYS [9] BUFFER PULLUP IO CELL STRENGTH /DOWN [12] (mA) [10] TYPE [11] Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 61

    ... AF18, AF24, Y17, AA17, AF22, A25, Y19, AA19, AE25, AF25, A20, Y20, A26, B26, AA20, A21, K26, U26, B21, H21, AE26, AF26 P21, Y21, AA21 Copyright © 2010–2011, Texas Instruments Incorporated (5) TYPE [4] BALL BALL RESET RESET POWER RESET REL. STATE REL. MODE ...

  • Page 62

    ... POWER RESET REL. STATE REL. MODE STATE [5] [6] [ GND vdds PWR PWR PWR Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com (continued) [8] HYS [9] BUFFER PULLUP IO CELL STRENGTH /DOWN [12] (mA) [10] TYPE [11 Yes 8 PU/PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 63

    ... IO D13 sdrc_d11 0 IO C13 sdrc_d12 0 IO B14 sdrc_d13 0 IO A14 sdrc_d14 0 IO B15 sdrc_d15 sdrc_d16 0 IO Copyright © 2010–2011, Texas Instruments Incorporated Table 2-27. [4] BALL RESET BALL RESET RESET REL. POWER STATE [5] REL. STATE MODE [7] [ vdds_mem vdds_mem vdds_mem vdds_mem ...

  • Page 64

    ... NA 4 PU/ PD LVCMOS ( PU/ PD LVCMOS ( PU/ PD LVCMOS ( PU/ PD LVCMOS ( PU/ PD LVCMOS ( PU/ PD LVCMOS ( PU/ PD LVCMOS (8) Yes 4 PU/ PD LVCMOS (8) Yes 4 PU/ PD LVCMOS (8) Yes 4 PU/ PD LVCMOS (8) Yes 4 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated [12] ...

  • Page 65

    ... IO safe_mode 7 T3 gpmc_d12 0 IO gpio_48 4 IO safe_mode 7 U2 gpmc_d13 0 IO gpio_49 4 IO safe_mode 7 V1 gpmc_d14 0 IO Copyright © 2010–2011, Texas Instruments Incorporated [4] BALL RESET BALL RESET RESET REL. POWER STATE [5] REL. STATE MODE [7] [ vdds_mem vdds_mem vdds_mem vdds_mem vdds_mem ...

  • Page 66

    ... Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS NA 8 PU/ PD LVCMOS NA 8 PU/ PD LVCMOS NA 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes NA PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated [12] ...

  • Page 67

    ... IO uart3_rx_irrx 2 I gpio_78 4 IO hw_dbg16 5 O safe_mode 7 F23 dss_data9 0 IO uart3_tx_irtx 2 O gpio_79 4 IO hw_dbg17 5 O Copyright © 2010–2011, Texas Instruments Incorporated [4] BALL RESET BALL RESET RESET REL. POWER STATE [5] REL. STATE MODE [7] [ vdds vdds vdds vdds vdds ...

  • Page 68

    ... LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS Yes 8 PU/ PD LVCMOS ( 10-bit DAC Copyright © 2010–2011, Texas Instruments Incorporated [12] ...

  • Page 69

    ... L24 cam_d6 0 I gpio_105 4 I safe_mode 7 K24 cam_d7 0 I gpio_106 4 I safe_mode 7 J23 cam_d8 0 I gpio_107 4 I safe_mode 7 Copyright © 2010–2011, Texas Instruments Incorporated [4] BALL RESET BALL RESET RESET REL. POWER STATE [5] REL. STATE MODE [7] [ vdda_dac vdda_dac vdda_dac vdda_dac vdds ...

  • Page 70

    ... Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS (1 (4) Yes 1 PU/ PD LVCMOS (1 (4) Yes 1 PU/ PD LVCMOS (1 (4) Yes 1 PU/ PD LVCMOS (1 (4) Yes 1 PU/ PD LVCMOS (1 (4) Yes 1 PU/ PD LVCMOS (1 (4) Yes 1 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated [12] ...

  • Page 71

    ... AA1 mmc2_dat7 0 IO mmc2_clkin 1 I mmc3_dat3 3 IO gpio_139 4 IO mm3_rxdm 6 IO safe_mode 7 V6 mcbsp3_dx 0 IO uart2_cts 1 I Copyright © 2010–2011, Texas Instruments Incorporated [4] BALL RESET BALL RESET RESET REL. POWER STATE [5] REL. STATE MODE [7] [ vdds_x vdds_x vdds vdds vdds ...

  • Page 72

    ... Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated [12] ...

  • Page 73

    ... IO uart2_cts 5 I safe_mode 7 W24 hsusb0_ data4 0 IO gpio_188 4 IO safe_mode 7 V23 hsusb0_ data5 0 IO gpio_189 4 IO safe_mode 7 Copyright © 2010–2011, Texas Instruments Incorporated [4] BALL RESET BALL RESET RESET REL. POWER STATE [5] REL. STATE MODE [7] [ vdds vdds vdds vdds H H ...

  • Page 74

    ... Open Drain 4 (10)(11) Yes 3 PU/ PD Open Drain 4 (10)(11) Yes 3 PU/ PD Open Drain 4 Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated [12] ...

  • Page 75

    ... AD18 sys_boot3 0 I dss_data20 3 O gpio_5 4 IO safe_mode 7 AC17 sys_boot4 0 I mmc2_dir_dat2 1 O dss_data21 3 O gpio_6 4 IO Copyright © 2010–2011, Texas Instruments Incorporated [4] BALL RESET BALL RESET RESET REL. POWER STATE [5] REL. STATE MODE [7] [ vdds vdds vdds vdds vdds ...

  • Page 76

    ... Yes NA PU/ PD LVCMOS NA 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes NA PU/ PD LVCMOS NA 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Copyright © 2010–2011, Texas Instruments Incorporated [12] ...

  • Page 77

    ... IO mm1_rxdm 5 IO hw_dbg11 7 O AC3 etk_d10 0 O uart1_rx 2 I hsusb2_clk 3 O gpio_24 4 IO hw_dbg12 7 O AC9 etk_d11 0 O Copyright © 2010–2011, Texas Instruments Incorporated [4] BALL RESET BALL RESET RESET REL. POWER STATE [5] REL. STATE MODE [7] [ vdds vdds vdds vdds vdds ...

  • Page 78

    ... Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com (1) (continued) [8] HYS [9] BUFFER PULLUP IO CELL STRENGTH /DOWN (mA) [10] TYPE [11] Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS Yes 4 PU/ PD LVCMOS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Copyright © 2010–2011, Texas Instruments Incorporated [12] ...

  • Page 79

    ... System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4) to modify the IO settings if required by the targeted interface application. (13) Mux0 if sys_boot6 is pulled down (clock master). Copyright © 2010–2011, Texas Instruments Incorporated [4] BALL RESET BALL RESET RESET REL. POWER ...

  • Page 80

    ... For the corresponding setting of the PBIASLITEPWRDNZ0 bit, see the System Control Module / SCM Programming Model / Extended-Drain I/Os and PBIAS Cells Programming Guide section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). 80 TERMINAL DESCRIPTION Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com ...

  • Page 81

    ... R23 NA R20 NA T22 NA M21 NA T23 NA M20 NA U22 NA N20 NA U23 NA K21 Copyright © 2010–2011, Texas Instruments Incorporated Section 2.5, Signal Description. For more information, see the Table 2-4. Multiplexing Characteristics CUS MODE 0 MODE 1 MODE 2 D7 sdrc_d0 C5 sdrc_d1 C6 sdrc_d2 B5 sdrc_d3 D9 sdrc_d4 D10 ...

  • Page 82

    ... MODE 5 MODE 6 safe_mo de_out1 safe_mo de_out1 gpio_34 safe_mo de gpio_35 safe_mo de gpio_36 safe_mo de gpio_37 safe_mo de gpio_38 safe_mo de gpio_39 safe_mo de gpio_40 safe_mo de gpio_41 safe_mo de gpio_42 safe_mo de gpio_43 safe_mo de safe_mo de gpio_44 safe_mo de gpio_45 safe_mo de gpio_46 safe_mo de Copyright © 2010–2011, Texas Instruments Incorporated MODE 7 ...

  • Page 83

    ... NA AG22 NA AE21 NA AH22 NA AE22 NA AG23 NA AE23 NA AH23 NA AE24 NA AG24 NA AD23 NA AH24 NA AD24 NA E26 NA G26 NA Copyright © 2010–2011, Texas Instruments Incorporated CUS MODE 0 MODE 1 MODE 2 R3 gpmc_d11 T3 gpmc_d12 U2 gpmc_d13 V1 gpmc_d14 V2 gpmc_d15 E2 gpmc_ncs0 NA gpmc_ncs1 NA gpmc_ncs2 D2 gpmc_ncs3 sys_ndmareq 0 F4 gpmc_ncs4 sys_ndmareq mcbsp4_clkx 1 G5 ...

  • Page 84

    ... Copyright © 2010–2011, Texas Instruments Incorporated MODE 7 ...

  • Page 85

    ... AG5 NA R10 NA AH5 NA T10 NA AH4 AG4 NA U10 NA AF4 AE4 NA V10 NA AH3 Copyright © 2010–2011, Texas Instruments Incorporated CUS MODE 0 MODE 1 MODE 2 J23 cam_d8 K23 cam_d9 F21 cam_d10 G21 cam_d11 C22 cam_xclkb F18 cam_wen cam_shutter J20 cam_strobe V20 mcbsp2_fsx T21 mcbsp2_clkx ...

  • Page 86

    ... Copyright © 2010–2011, Texas Instruments Incorporated MODE 7 ...

  • Page 87

    ... NA AE20 NA AE17 NA AF19 NA AF17 NA AF20 NA AF25 NA W15 NA AF26 NA V16 NA AH25 NA V13 NA Copyright © 2010–2011, Texas Instruments Incorporated CUS MODE 0 MODE 1 MODE 2 T24 hsusb0_data0 uart3_tx_irtx T23 hsusb0_data1 uart3_rx_irrx U24 hsusb0_data2 uart3_rts_sd U23 hsusb0_data3 uart3_cts_rctx W24 hsusb0_data4 V23 hsusb0_data5 W23 hsusb0_data6 T22 ...

  • Page 88

    ... Copyright © 2010–2011, Texas Instruments Incorporated MODE 7 ...

  • Page 89

    ... A15, A18 A12, D16, C16, B18, A18, B22, A22, G28, C28 AA16 NA U14 NA AA14 NA W14 NA Copyright © 2010–2011, Texas Instruments Incorporated CUS MODE 0 MODE 1 MODE 2 AC11 etk_d14 AD12 etk_d15 F12, F13, vdd_core G12, G13, H12, H13, J17, J18, K17, K18, ...

  • Page 90

    ... N24 vdds_mmc1 H8 vdds_x NA vdds N20 cap_vddu_arr ay NA vss NA vss NA vdds NA vss NA vdds U8 cap_vdd_sra m_mpu_iva H17 cap_vdd_sra m_core W15 sys_xtalgnd Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com MODE 3 MODE 4 MODE 5 MODE 6 Copyright © 2010–2011, Texas Instruments Incorporated MODE 7 ...

  • Page 91

    ... GPMC output address bit 6 / extended multiplexed address gpmc_a22 gpmc_a7 GPMC output address bit 7 / extended multiplexed address gpmc_a23 gpmc_a8 GPMC output address bit 8 / extended multiplexed address gpmc_a24 Copyright © 2010–2011, Texas Instruments Incorporated NOTE TYPE BALL BALL BALL BOTTOM [3] BOTTOM TOP (CBC Pkg.) [4] ...

  • Page 92

    ... N1 AC1 AE5 AD6 AD5 AC5 IO H2 AB3 AC3 Y1 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com (1) (continued) BALL TOP BALL SUBSYSTEM (CBC Pkg.) [5] BOTTOM PIN (CUS MULTIPLEXING Pkg.) [ gpmc_d8 T1 G2 gpmc_d9 - / N1 NA ...

  • Page 93

    ... NA in table stands for "Not Applicable". For more information, see Memory Subsystem / SDRAM Controller (SDRC) Subsystem / SDRC Subsystem Environment section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). Copyright © 2010–2011, Texas Instruments Incorporated TYPE BALL BALL BALL BOTTOM ...

  • Page 94

    ... B18 NA AA18 C18 NA V20 D18 NA G20 A4 NA K20 B4 NA J20 D6 NA J21 B3 NA U21 B2 NA R20 C3 NA M21 E3 NA M20 F6 NA N20 E10 NA K21 E9 NA Y16 E7 NA N21 G6 NA R21 G7 NA AA15 F7 NA Y12 F9 Copyright © 2010–2011, Texas Instruments Incorporated [4] ...

  • Page 95

    ... Data Strobe 1 sdrc_dqs2 Data Strobe 2 sdrc_dqs3 Data Strobe 3 ( this table stands for "Not Applicable". (2) For a list of pins not supported on a particular package, see Copyright © 2010–2011, Texas Instruments Incorporated [3] BALL BALL TOP BALL BOTTOM BOTTOM (CBP Pkg.) (CBC Pkg.) (CBP Pkg ...

  • Page 96

    ... AE21 / M24 AC19 / G24 AE22 / M26 AB19 / H23 AE23 / F25 AD20 / D23 AE24 / N24 AC20 / K22 AD23 / AC25 AD21 / V21 AD24 / AB25 AC21 / W21 G26 D24 H25 E23 H26 E24 J26 F23 AC26 AC22 Copyright © 2010–2011, Texas Instruments Incorporated [4] ...

  • Page 97

    ... LCD rfbi_hsync0 Hsync for 1st LCD rfbi_te_vsync tearing effect removal and Vsync input 1 from 2nd LCD rfbi_hsync1 Hsync for 2nd LCD rfbi_cs1 2nd LCD chip select Copyright © 2010–2011, Texas Instruments Incorporated [2] TYPE [3] BALL BOTTOM (CBP Pkg.) O AD27 O AB28 O ...

  • Page 98

    ... TYPE [3] BALL BOTTOM (CBP Pkg.) [4] AO Y28 AO W28 AO Y27 AO W27 AIO W26 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com BALL BOTTOM BALL BOTTOM (CBC Pkg.) [4] (CUS Pkg.) [4] W26 AB24 V26 AA23 W25 ...

  • Page 99

    ... For more information, see Multi-Channel Buffered Serial Port / McBSP Environment section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). Table 2-14. Serial Communication Interfaces – McBSP LP Signals Description SIGNAL NAME DESCRIPTION [2] [1] MULTICHANNEL SERIAL (McBSP LP 1) Copyright © 2010–2011, Texas Instruments Incorporated TYPE [3] BALL BOTTOM (CBP Pkg.) [4] IOD J25 ...

  • Page 100

    ... IO AB4 IO AA4 IO AC2 O AC3 O AB1 O AB2 IO AA3 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com BALL BOTTOM BALL BOTTOM (CBC Pkg.) [4] (CUS Pkg.) [4] T20 Y18 U19 / W19 V17 AB20 U17 W18 T17 V18 ...

  • Page 101

    ... High-Speed USB Host Subsystem / High-Speed USB Host Subsystem Environment section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). Table 2-17. Serial Communication Interfaces – USB Signals Description SIGNAL NAME DESCRIPTION [1] HIGH-SPEED UNIVERSAL SERIAL BUS INTERFACE (HSUSB0) Copyright © 2010–2011, Texas Instruments Incorporated TYPE [3] BALL BOTTOM (CBP Pkg.) [4] O ...

  • Page 102

    ... AE7 O AF7 I AG7 I AH7 IO AG8 IO AH8 IO AB2 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com Section 4.3.6 (continued) BALL BOTTOM BALL BOTTOM [4] (CBC Pkg.) [4] (CUS Pkg.) [4] W19 R21 U20 R23 V19 P23 W18 ...

  • Page 103

    ... Dedicated for external transceiver Bidirectional data bus additional signals for 12-pin ULPI operation • this table stands for "Not applicable". • This pin is not supported on the CUS package. Copyright © 2010–2011, Texas Instruments Incorporated [2] TYPE BALL BOTTOM [3] (CBP Pkg.) IO ...

  • Page 104

    ... AE4 / AE11 IO AH3 / AH9 IO AF3 / AF13 IO AE3 / AE13 IO AF11 IO AG9 IO AF9 IO AH14 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com BALL BOTTOM BALL BOTTOM (CBC Pkg.) [4] (CUS Pkg.) [4] N19 M23 L18 L23 M19 ...

  • Page 105

    ... Test Clock jtag_rtck ARM Clock Emulation jtag_tms_tmsc Test Mode Select jtag_tdi Test Data Input jtag_tdo Test Data Output jtag_emu0 Test emulation 0 jtag_emu1 Test emulation 1 Copyright © 2010–2011, Texas Instruments Incorporated TYPE [3] BALL BOTTOM (CBP Pkg.) [4] O AE10 O AF10 O AF11 O AG12 ...

  • Page 106

    ... AD2/B21 D25/AE3 AC8/F21 E26/AD2 AD9/G21 A23/AA4 AC4/F18 D26/V2 AD5/J20 G25/AE4 AC3/G22 K24/AF6 AC9/E22 G26/AE6 AC10/D24 H25/AF7 AD11/E23 H26/AF9 AC11/E24 J26/AE9 AD12/F23 BALL BOTTOM BALL BOTTOM (CBC Pkg.) [4] (CUS Pkg.) [ AD21 Y24 AA24 AD22 Copyright © 2010–2011, Texas Instruments Incorporated [6] ...

  • Page 107

    ... General-purpose IO 40 gpio_41 General-purpose IO 41 gpio_42 General-purpose IO 42 gpio_43 General-purpose IO 43 gpio_44 General-purpose IO 44 gpio_45 General-purpose IO 45 gpio_46 General-purpose IO 46 gpio_47 General-purpose IO 47 Copyright © 2010–2011, Texas Instruments Incorporated TYPE [3] BALL BOTTOM (CBP Pkg.) [4] IO AF26 IO AF25 IO AH26 IO AG26 IO AE14 ...

  • Page 108

    ... AA28 IO AA27 IO G25 IO H27 IO H26 IO H25 IO E28 IO J26 IO AC27 IO AC28 IO A24 IO A23 IO C25 IO C27 IO C23 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com (1) (continued) BALL BOTTOM BALL BOTTOM (CBC Pkg.) [4] (CUS Pkg.) [ AD1 ...

  • Page 109

    ... General-purpose IO 142 gpio_143 General-purpose IO 143 gpio_144 General-purpose IO 144 gpio_145 General-purpose IO 145 gpio_146 General-purpose IO 146 gpio_147 General-purpose IO 147 gpio_148 General-purpose IO 148 gpio_149 General-purpose IO 149 Copyright © 2010–2011, Texas Instruments Incorporated TYPE [3] BALL BOTTOM (CBP Pkg.) [4] I AG17 I AH17 IO B24 IO C24 IO D24 ...

  • Page 110

    ... V3 IO AE15 IO AF14 IO AG14 IO AE22 IO U25 IO V28 IO V27 IO V26 Table 2-1 and Table 2-4. Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com (1) (continued) BALL BOTTOM BALL BOTTOM (CBC Pkg.) [4] (CUS Pkg.) [4] W2 AC2 ...

  • Page 111

    ... C16 / B18 / A18 / B22 / A22 / G28 / vdda_dpll_per Input power for the analog part of the Peripheral DPLLs vdda_wkup_bg_bb For wakeup LDO and VDDA (2 LDOs SRAM and BG) Copyright © 2010–2011, Texas Instruments Incorporated BALL TOP BALL BOTTOM (2) [4] (CBP Pkg.) [5] (CBC Pkg ...

  • Page 112

    ... P13/P12/ P11/ P10/ P8/ N16/ N15/ N14/ N13/ N12/ N11/ N10/ N9/ M16/ M13/ M11/ M10/ M9/ L17/ L13/ L10/ L8/ K15/ K14/ K11/ K10/ J16/ J15/ J14/ J13/ J12/ J11/H16/ H14/ H11 NA AA12 NA N24 H17 N20 N21 NA W15 Copyright © 2010–2011, Texas Instruments Incorporated [4] ...

  • Page 113

    ... DDR Supply NC No Connect f-vdd Flash Supply f-vdd Flash Supply NC No Connect NC No Connect f-vdd Flash Supply f-vdd Flash Supply Copyright © 2010–2011, Texas Instruments Incorporated [2] TYPE [3] BALL BALL TOP BOTTOM (CBP Pkg.) (CBP Pkg.) [4] I AE25 AI-I AE17 AO AF17 ...

  • Page 114

    ... A27 A23 A28 AB1 AG1 AB23 AG28 AC1 AH1 AC2 AH2 AC22 AH27 AC23 AH28 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com pop_y9_af10 pop_aa10_af12 pop_aa11_af13 pop_aa12_af14 pop_aa13_af15 pop_y14_af17 pop_aa14_af16 pop_b16_a20 pop_y17_af21 pop_aa17_af18 ...

  • Page 115

    ... Shared Ground vss Shared Ground vss Shared Ground vss Shared Ground vss Shared Ground (1) For more details on the feedthrough pin connections, please refer to the PoP memory datasheet. Copyright © 2010–2011, Texas Instruments Incorporated B1 B1 B23 B28 AB11 AG13 AC14 AH16 AA2 ...

  • Page 116

    ... HBM (Human CAM (2) Body Model) (8) GPMC Other signals (3) CDM (Charged Device Model) (5) to determine the ball information per package. Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com MIN MAX UNIT –0.5 1.5 V –0.5 1 ...

  • Page 117

    ... AM3715 (800M Hz): @1.27V (6) This maximum vdd_mpu_iva current is observed at OPP1G operating point. (7) Depending on the microprocessor chosen, the IVA feature may or may not be supported. See the on device features. Copyright © 2010–2011, Texas Instruments Incorporated PARAMETER DESCRIPTION Processors Core Submit Documentation Feedback ...

  • Page 118

    ... AM3715 AM3703 www.ti.com Table 3-4. The POH OPP1G MAX TIME Not available 25K(1) 75K NOM MAX UNIT (1) See (1) See 1.80 1. 1.80 1. 1.80 1.91 V 3.00 to 3.30 3. 150 1.80 1.91 V 3.00 3. 150 1.80 1. 1.80 1. 1.80 1. 1.80 1. Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 119

    ... Ground for video buffers and DAC vss Main ground T Operating junction temperature J range (1) See Section 4.3.4, Processor Clocks. OPP voltage values may change following the silicon characterization result. Copyright © 2010–2011, Texas Instruments Incorporated MIN 1.71 Commercial 0 Temperature Industrial Temperature -40 Extended Temperature -40 ...

  • Page 120

    ... OH 0.05 Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com Table 3-5 NOM MAX UNIT 0.3 * vdds_mem vdds_mem 0.2 * vdds_mem 1. 1. vdds_mmc1 + 0.3 0.30 * vdds_mmc1 0 vdds_mmc1 + 0.3 0.25 * vdds_mmc1 0.125 * vdds_mmc1 Copyright © 2010–2011, Texas Instruments Incorporated have ...

  • Page 121

    ... B (5) t Output rise time with a capacitive load from 150 pF ROUT with internal pullup Fast Mode V High-level input voltage IH V Low-level input voltage IL Copyright © 2010–2011, Texas Instruments Incorporated MIN evaluated Normal Mode (SPEEDCTRL ( High-Speed (SPEEDCTRL ( 0.70 * vdds_x –0.3 ...

  • Page 122

    ... AM3715 AM3703 www.ti.com NOM MAX 0.2 * vdds 10 10 250 B 250 B vdds + 0.5 0.3 * vdds 0.2 * vdds vdds 0.3 * vdds 0.45 1. (14) (14) vdds_x + 0.3 (14) 0.35 * vdds_x 1.3 10 vdds + 0.3 0.35 * vdds 0.45 Copyright © 2010–2011, Texas Instruments Incorporated UNIT V V μ μ ...

  • Page 123

    ... For a full description of the DS0 load compensation register configuration, see the description of the CONTROL_PROG_IO1 configuration registers in System Control Module / Programming Model / Feature Settings / SDRC I/O Drive Strength Selection section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). Copyright © 2010–2011, Texas Instruments Incorporated MIN 1.00 ...

  • Page 124

    ... Electrical Characteristics = ( (DX) (DY) Ball Characteristics Section 2.4, Multiplexing Characteristics table. Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com is larger than the maximum single-ended IL )/2. Common mode ripple may be due to section, column “BUFFER DRIVE ...

  • Page 125

    ... C vdda_dac (1) In power plan configuration. (2) The typical value corresponds to 4 capacitors of 100 nF. (3) The typical value corresponds to 7 capacitors of 100 nF. (4) In power rail configuration. Copyright © 2010–2011, Texas Instruments Incorporated MIN 0.6 0.6 MIN TYP 200 400 350 ...

  • Page 126

    ... C cap_vddu_array C cap_vdd_bb_mpu_iva 126 Electrical Characteristics MIN TYP 0.7 1 0.7 1 0.7 1 0.7 1 0.7 1 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com MAX UNIT 1.3 μF 1.3 μF 1.3 μF 1.3 μF 1.3 μF ...

  • Page 127

    ... Cvdds_mmc1 vdds_mem vdds_mem Cvdds_mem vdda_wkup_bg_bb vdda_wkup_bg_bb Cvdda_wkup_bg_bb cap_vdd_bb_mpu_iva Ccap_vdd_bb_mpu_iva cap_vddu_wkup_logic Ccap_vddu_wkup_logic cap_vddu_array Ccap_vddu_array vdds vdds Cvdds Copyright © 2010–2011, Texas Instruments Incorporated Device Video DAC SRAM_LDO1 cap_vdd_sram_mpu_iva SRAM_LDO2 cap_vdd_sram_core DPLL_MPU DPLL_CORE MMC I/Os DLL DPLL5 VDDS_MEM BG DPLL4 BBLDO WKUP_LOGIC ...

  • Page 128

    ... Description / PRCM Reset Manager Functional Description / Reset Sequences of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). Figure 3-2 shows the power-up sequence. 128 Electrical Characteristics NOTE NOTE NOTE Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com ...

  • Page 129

    ... Turn off all reference domains (vdda_wkup_bg_bb) – Turn off all standard IO domains (vdds, vdds_mem) Figure 3-3 shows both power-down sequences: one of them is described in black color, and the other one in dash style blue. Copyright © 2010–2011, Texas Instruments Incorporated 1.8 V 1.8 V (1) 1.1 V (1) 1 ...

  • Page 130

    ... IO domains shut down and vdda_sram shuts down. 130 Electrical Characteristics Figure 3-3. Power-Down Sequence Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 131

    ... Oscillator is used sys_xtalin sys_clkreq Copyright © 2010–2011, Texas Instruments Incorporated NOTE From power IC: 32 768-Hz Alternate clock source selectable (48-MHz, 54-MHz) To peripherals (from oscillator clock [sys_xtalin]): 12-,13-, 16.8-, 19.2-, 26-, or 38.4-MHz (no divider) To peripherals (from oscillator clock [sys_xtalin]): 12-,13-, 16 ...

  • Page 132

    ... Crystal ±50 ppm (±5 (1) ppm) Square ±50 ppm (±5 (1) ppm) +/-50 ppm Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com (4) DUTY CYCLE JITTER TRANSITION - - < (2) 45 (3) tc(xtalin) - 200ps 49% to 51% < Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 133

    ... When selecting a crystal, the system design must take into account the temperature and aging characteristics of a crystal versus the user environment and expected lifetime of the system. Copyright © 2010–2011, Texas Instruments Incorporated Figure 4-2 describes the crystal implementation. Device ...

  • Page 134

    ... The switching time in this case is about 100 μs. 134 Clock Specifications MIN 12, 13, 16.8, or 19.2 3 parameter. sX MIN 12, 13, 16.8, 19.2, 26, or 38.4 1.00 160 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com TYP MAX UNIT MHz ms TYP MAX ...

  • Page 135

    ... CK0 Frequency, sys_32k c(32k) t Rise time, sys_32k R(32k) t Fall time, sys_32k F(32k) t Frequency stability, sys_32k J(32k) Copyright © 2010–2011, Texas Instruments Incorporated MIN 12, 13, 16.8, 19.2, 26, or 38.4 0. c(xtalin) (1) , sys_xtalin OSC0 MIN 3 MIN Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 AM3715, AM3703 SPRS616F – ...

  • Page 136

    ... ALT0 Figure 4-5. sys_altclk Input Clock Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com CK1 CK1 SWPS038-009 TYP MAX UNIT MHz 1 MΩ (2) TYP MAX UNIT MHz 0. c(altclk ppm ALT1 ALT1 SWPS038-010 Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 137

    ... Fall time, sys_clkout1 F(CLKOUT1) (1) SC[0: Load capacitance L t Peak-to-peak jitter J t Cycle-to-cycle jitter JC2C t Pulse duration, sys_clkout1 low or high W(CLKOUT1) t Rise time, sys_clkout1 R(CLKOUT1) Copyright © 2010–2011, Texas Instruments Incorporated MIN sys_xtalin / sys_xtalout clock frequency MIN sys_xtalin/sys_xtalout clock frequency 4 0.45* tc(CLKOUT 1) (2) (4) ...

  • Page 138

    ... Product Folder Link(s): AM3715 AM3703 www.ti.com (6) (continued) TYP MAX UNIT ( CO1 CO1 SWPS038-011 TYP MAX UNIT ( MHz (2) MHz, 96 MHz Ω (8) TYP MAX UNIT ( MHz (4) MHz, 96 MHz 1 / sys_xtalin ns (MHz core_dpll ns (MHz) 18.52 ns 10.42 ns 0.51*tc(clkout ns 2) Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 139

    ... The applicative subsystem integrates five DPLLs and a DLL. The PRM and CM drive those listed below. The main DPLLs are: • DPLL1 (MPU) • DPLL3 (Core) • DPLL4 (Peripherals) • DPLL5 (Second peripherals DPLL) Copyright © 2010–2011, Texas Instruments Incorporated MIN Source clock: sys_xtalin Source clock: core_dpll Source clock: 54MHz Source clock: 96MHz (1) 1.5 (1) 1 ...

  • Page 140

    ... DPLL in normal mode: 120*REFCLK lowcurrstdby = 0 MAX UNIT COMMENTS 1. MHz FINP 2.5 MHz REFCLK 800 MHz (2) 2000 MHz [ 1)] * FINP * [1 / M2] 2000 MHz [ 1)] * FINP 350*REFCLK μs 500*REFCLK μs 7.5 + μs DPLL in low-power mode: 30*REFCLKs lowcurrstdby = 1 Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 141

    ... Input clock frequency input t Lock time lock t Relock time (Mode transitions through idle relock mode) (1) Maximum frequency for nominal conditions. Copyright © 2010–2011, Texas Instruments Incorporated MIN TYP (3) (Fast Table 4-16. DLL Characteristics MIN TYP 1.71 1.8 66 120 250 1 ...

  • Page 142

    ... AM3715 AM3703 www.ti.com Noise Filter vdda_dplls_dll C Noise Filter vdda_dpll_per C 030-017 TYP MAX UNIT 100 150 nF TM (3) OPP130 MAX MIN TYP MAX 1.2 1.21 1.27 1.33 TM (4) (4) (5)(6) OPP130 OPP1G TYP MAX MIN TYP MAX Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 143

    ... PRCM Functional Description / PRCM Clock Manager Functional Description / Clock Configurations / Processor Clock Configurations section or the MPU Subsystem / MPU Subsystem Integration / MPU Subsystem Clock and Reset Distribution / Clock Distribution section of the AM/DM37x Multimedia Device Technical Reference Manual (SPRUGN4). Copyright © 2010–2011, Texas Instruments Incorporated OPP100 1.02 1 ...

  • Page 144

    ... MAX 1.08 1.14 1.20 OPP100 Ratio Max Ratio Max Ratio Freq.(MH Freq.( 664 - 532 - 2 *(M2 = 332 2 *(M2 = 266 2 *(M2 = (1) ( 332 1 266 1 (1) (1) 2 166 2 133 2 ( 166 1 133 1 (1) ( 66.5 2 MAX 1.20 Copyright © 2010–2011, Texas Instruments Incorporated (1) (1) (1) (1) ...

  • Page 145

    ... SGX – Option 3 SGX_192M_FCLK (1) This ratio is configurable by software programming. For more information, see the AM/DM37x Multimedia Device Technical Reference Manual (SPRUGN4). (2) SGX (Graphic Accelerator) is not available in OPP50 operating point. Copyright © 2010–2011, Texas Instruments Incorporated Max Freq Max Freq Ratio (MHz) ...

  • Page 146

    ... Section vssa_dac vdda_dac cvideo1_out I DAC + TVBUF – R OUT cvideo1_vfb TVDET VREF cvideo1_rset R SET = External pin Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com 5.4, Electrical Specifications Over R LOAD swps038-125 Mode(1) Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 147

    ... Recommended Operating Conditions. AVDAC Figure 5-2. Recommended Loading Conditions for TVOUT Bypass (1) In single-channel configuration only channel-1 is used. Copyright © 2010–2011, Texas Instruments Incorporated Mode Specifications (DAC-Only) Figure 5-2 shows the connection. For more information regarding ...

  • Page 148

    ... LOAD1LOAD2 148 Video DAC Specifications Mode Specifications (DAC-Only) Figure 5-3 shows the connection. For more information regarding Section Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com Electrical Specifications Over 5.4, Electrical Specifications Over ...

  • Page 149

    ... R Output impedance VOUT REFERENCE V Internal Band Gap Voltage Reference REF Copyright © 2010–2011, Texas Instruments Incorporated NOTE CONDITIONS/ASSUMPTIONS 50 to 111 input code range 111 to 895 input code range 783 to 1007 input code range 111 to 895 input code range 0 to 1023 input ...

  • Page 150

    ... Management Figure 5-4. NOTE Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com (8) (continued) MIN TYP MAX UNIT 4.5 6.5 8 CLK μA 90 180 270 μA μ μA . CLK , and the digital supply VDD. CLK Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 151

    ... The SNR value is for dc coupling. (4) PSR measures the effect of a supply disturbance at cvideo1_out and cvideo2_out. (5) The flat band measurement is done at 500 kHz for characterizing the attenuation at 5.1 MHz. (6) For more information on code range definition, see Copyright © 2010–2011, Texas Instruments Incorporated DC mode AC mode DC mode ...

  • Page 152

    ... Figure 5-4 for more details on the relation between the composite NOTE Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com Peak level White level Black level Blanking level Sync level SWPS038-130 Levels(1)(2) Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 153

    ... The DAC Power Supply Rejection Ratio (PSRR) is defined as the relative variation of the full-scale output current divided by the supply variation. Thus expressed in percentage of Full-Scale Range (FSR) per volt of supply Depending on frequency, the PSRR is defined in Copyright © 2010–2011, Texas Instruments Incorporated CONDITIONS/ASSUMPTIONS 37 to 954 input code range 1.5 kΩ LOAD 37 to 954 input code range 1.5 kΩ ...

  • Page 154

    ... Decreases 20 dB/dec. Example MHz the maximum Table Maximum Supply Noise Density < 20 µV / √Hz Decreases 20 dB/dec. Example MHz the maximum noise density is 2 µV / √Hz Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com 5-6. PP 5-7 ...

  • Page 155

    ... Environment / TV Display Support section of AM/DM37x Technical Reference Manual (literature number SPRUGN4). Figure 5-6. cvideo_out1 and cvideo_ou2 Transfer Function The dc levels (Voffset) will be shifted due to process variations. Copyright © 2010–2011, Texas Instruments Incorporated and can be expressed as: DACMAX from the DAC is given by: ...

  • Page 156

    ... Minimum pulse duration = Typical pulse duration - maximum duty cycle error 156 Timing Requirements and Switching Characteristics Tn Figure 6-1. Cycle (or Period) Jitter NOTE Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com Tn+1 SWPS038-013 Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 157

    ... Copyright © 2010–2011, Texas Instruments Incorporated Table 6-1. Timing Parameters SUBSCRIPTS PARAMETER Cycle time (period) Delay time Disable time Enable time Hold time Setup time Start bit Transition time Valid time Pulse duration (width) Unknown, changing, or don’t care level ...

  • Page 158

    ... Figure 6-6). OPP100 MIN 2.3 1.5 (2) valid before 2.3 (2) valid after output 1.9 OPP100 MIN 0.5P 0.5P Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com VALUE UNIT 1 (1) OPP50 UNIT MAX ...

  • Page 159

    ... Delay time, output clock gpmc_clk rising edge to d(clkH-iodir) output IO direction control gpmc_io_dir high (IN direction) F24 t Delay time, output clock gpmc_clk rising edge to d(clkH-iodirIV) output IO direction control gpmc_io_dir low (OUT direction) Copyright © 2010–2011, Texas Instruments Incorporated (16) , output clock gpmc_clk (6) F (11) transition (5) E (11) ...

  • Page 160

    ... ClkActivationTime – multiple of 3) (14) (14) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime (14) otherwise (14) if ((OEOnTime – ClkActivationTime multiple of 3) Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com (14) (14) (14) (14) ...

  • Page 161

    ... GPMC controller. For a full description of the gpmc_io_dir feature, see the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). (18) See Section 4.3.4, Processor Clocks. Copyright © 2010–2011, Texas Instruments Incorporated (14) if ((OEOnTime – ClkActivationTime – multiple of 3) (14) if ((OEOnTime – ClkActivationTime – multiple of 3) ...

  • Page 162

    ... Figure 6-2. GPMC/NOR Flash—Synchronous Single Read—(GpmcFCLKDivider = 0) 162 Timing Requirements and Switching Characteristics F18 Valid Address F19 F19 F8 F8 F20 OUT Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com F10 F11 F13 F12 D 0 F23 F24 ...

  • Page 163

    ... F6 gpmc_nbe0_cle gpmc_nbe1 F6 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir (1) In gpmc_ncsx equal (2) In gpmc_waitx equal Figure 6-3. GPMC/NOR Flash—Synchronous Burst Read—4x16-bit (GpmcFCLKDivider = 0) Copyright © 2010–2011, Texas Instruments Incorporated Valid Address F8 F8 F21 OUT OUT Timing Requirements and Switching Characteristics Submit Documentation Feedback ...

  • Page 164

    ... Figure 6-4. GPMC/NOR Flash—Synchronous Burst Write—(GpmcFCLKDivider > 0) 164 Timing Requirements and Switching Characteristics F17 F17 F8 F8 F14 F14 F15 D 0 OUT Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com F3 F17 F17 F17 F17 F9 F15 F15 ...

  • Page 165

    ... F4 gpmc_a[16:1] Address (LSB) (gpmc_d[15:0]) gpmc_nadv_ale gpmc_noe gpmc_waitx gpmc_io_dir (1) In gpmc_ncsx equal (2) In gpmc_waitx equal Figure 6-5. GPMC/Multiplexed NOR Flash—Synchronous Burst Read Copyright © 2010–2011, Texas Instruments Incorporated F2 Valid Valid Address (MSB F10 F23 OUT OUT Timing Requirements and Switching Characteristics ...

  • Page 166

    ... Timing Requirements and Switching Characteristics F18 Address (MSB) F17 F17 F8 F8 F20 F14 F15 F22 F21 OUT Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com F3 F17 F17 F17 F17 F9 F14 F15 F15 SWPS038-018 ...

  • Page 167

    ... The internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field. (2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally. (3) GPMC_FCLK is general-purpose memory controller internal functional clock. (4) See Section 4.3.4, Processor Clocks. Copyright © 2010–2011, Texas Instruments Incorporated Figure 6-7 through Figure 6-12). OPP100 ...

  • Page 168

    ... B + 2.0 B – 0 2.6 (3) (3) ( 2.0 C – 0 2.6 (9) (9) ( 2.0 J – 0 2.6 (9) (9) ( 2.0 J – 0 2.6 (10) (10) (10) + 2.0 K – 0 2.6 (11) (11) (11 2.0 L – 0 2.6 (11) (11) (11 2.0 L – 0 2.6 (14) (14) (14) + 2.0 M – 0 2.6 Copyright © 2010–2011, Texas Instruments Incorporated UNIT ...

  • Page 169

    ... GPMC controller. For a full description of the gpmc_io_dir feature, see the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). (15) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. (16) See Section 4.3.4, Processor Clocks. Copyright © 2010–2011, Texas Instruments Incorporated MIN (13) (8) I – 0.2 ...

  • Page 170

    ... Figure 6-7. GPMC / NOR Flash—Asynchronous Read—Single Word 170 Timing Requirements and Switching Characteristics FA5 FA1 Valid Address FA0 Valid FA0 Valid FA4 FA13 FA15 FA14 OUT Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com Data IN 0 Data OUT SWPS038-019 Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 171

    ... From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field. (3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Figure 6-8. GPMC / NOR Flash—Asynchronous Read—32-bit Copyright © 2010–2011, Texas Instruments Incorporated FA1 FA16 FA9 ...

  • Page 172

    ... Figure 6-9. GPMC / NOR Flash—Asynchronous Read—Page Mode 4x16-bit 172 Timing Requirements and Switching Characteristics FA20 FA21 FA1 Add0 Add1 FA0 FA0 FA18 FA13 D0 FA15 FA14 Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com FA20 FA20 Add2 Add3 Add4 SWPS038-021 Copyright © 2010–2011, Texas Instruments Incorporated D3 OUT ...

  • Page 173

    ... FA12 gpmc_nadv_ale gpmc_nwe FA29 gpmc_d[15:0] gpmc_waitx gpmc_io_dir (1) In gpmc_ncsx equal gpmc_waitx equal Figure 6-10. GPMC / NOR Flash—Asynchronous Write—Single Word Copyright © 2010–2011, Texas Instruments Incorporated FA1 Valid Address FA0 FA0 FA3 FA27 FA25 Data OUT OUT Timing Requirements and Switching Characteristics ...

  • Page 174

    ... Figure 6-11. GPMC / Multiplexed NOR Flash—Asynchronous Read—Single Word 174 Timing Requirements and Switching Characteristics FA1 FA5 Address (MSB) FA0 Valid FA0 Valid FA4 FA13 FA37 FA15 FA14 Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com Data IN Data IN OUT IN SWPS038-023 Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 175

    ... FA29 gpmc_a[16:1] Valid Address (LSB) (gpmc_d[15:0]) gpmc_waitx gpmc_io_dir (1) In gpmc_ncsx equal gpmc_waitx equal Figure 6-12. GPMC / Multiplexed NOR Flash—Asynchronous Write—Single Word Copyright © 2010–2011, Texas Instruments Incorporated FA1 Address (MSB) FA0 FA0 FA27 FA25 FA28 OUT Timing Requirements and Switching Characteristics ...

  • Page 176

    ... AM3715 AM3703 www.ti.com 6-16). VALUE UNIT 1 (1) (2) (4) OPP50 MAX MIN MAX 6.5 9.1 4.0 5.6 6.5 9.1 6.5 9.1 6.5 9.1 6.5 9.1 6.5 9.1 100 170 (4) OPP50 MAX MIN MAX (2) ( Copyright © 2010–2011, Texas Instruments Incorporated UNIT UNIT ns ...

  • Page 177

    ... L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK (12 ((CSRdOffTime – OEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – OEExtraDelay)) * GPMC_FCLK (13) In gpmc_ncsx equal (14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. (15) See Section 4.3.4, Processor Clocks. Copyright © 2010–2011, Texas Instruments Incorporated OPP100 MIN (1) A (13) (2) B – ...

  • Page 178

    ... Timing Requirements and Switching Characteristics GNF1 GNF2 GNF0 GNF3 Command GNF1 GNF7 GNF9 GNF0 GNF3 Address Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com GNF6 GNF5 GNF4 SWPS038-025 GNF6 GNF8 GNF4 SWPS038-026 ...

  • Page 179

    ... Figure 6-15. GPMC / NAND Flash—Data Read Cycle GPMC_FCLK gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe gpmc_nwe gpmc_a[16:1] (gpmc_d[15:0]) (1) In gpmc_ncsx equal Figure 6-16. GPMC / NAND Flash—Data Write Cycle Copyright © 2010–2011, Texas Instruments Incorporated GNF12 GNF10 GNF14 GNF13 DATA GNF1 GNF9 GNF0 GNF3 DATA ...

  • Page 180

    ... Timing Requirements and Switching Characteristics NOTE show the LPDDR interface schematics for a LPDDR memory system. The 1 Figure 6-17 except that the high word LPDDR device is Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 181

    ... Figure 6-17. AM37x LPDDR High Level Schematic (x16 memories) Copyright © 2010–2011, Texas Instruments Incorporated T DQ0 T DQ7 T LDM T LDQS T DQ8 T DQ15 T UDM T UDQS LPDDR ...

  • Page 182

    ... DQ24 T DQ31 T DM3 T DQS3 T BA0 T BA1 A14 T CS N/C T CAS T RAS CKE N MIN MAX LPDDR-266 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com LPDDR UNIT NOTES (1) See Note Bits (2) Devices See Note Balls ...

  • Page 183

    ... The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For 1x16 and 1x32 LPDDR memory systems, the second LPDDR device is omitted from the placement. Copyright © 2010–2011, Texas Instruments Incorporated TYPE Signal ...

  • Page 184

    ... Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com UNIT NOTES (1) (2) Mils See Notes , (1) (2) Mils See Notes , (1) (2) (3) Mils See Notes , , (4) See Note (5) w See Note 6-20. The size of this region varies with Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 185

    ... No terminations of any kind are required in order to meet signal integrity and overshoot requirements. Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only type permitted. Table 6-19 shows the specifications for the series terminators. Copyright © 2010–2011, Texas Instruments Incorporated A1 LPDDR Device A1 Figure 6-20. LPDDR Keepout Region Table 6-18 Table 6-17 ...

  • Page 186

    ... See Notes , , MAX UNIT NOTES 2w 25 Mils See Note 25 Mils See Note CACLM+50 Mils See Note 100 Mils 100 Mils See Note See Note 100 Mils See Note 100 Mils Copyright © 2010–2011, Texas Instruments Incorporated (1) (2) (3) (2) (2) (1) ...

  • Page 187

    ... DQLM is the longest Manhattan distance of the DQS and DQ net classes. (4) There is no need, and it is not recommended, to skew match across data bytes. This specification is only relative within a data byte. (5) DQs from other bytes are considered other LPDDR traces. Copyright © 2010–2011, Texas Instruments Incorporated T E0 ...

  • Page 188

    ... P (4) 0.93 (4) 0.93 Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com data goes directly to memory. OPP50 UNIT MIN MAX 216 MHz (2) 0.5P ns (2) 0.5P ns (2) - 2.083 0 2.083 ps (2) (2) 0.044 * P ps 0.93 ns 0.93 ns Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 189

    ... The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified. ( (Data bus size is limited to 8 bits. So the bits configuration is either cam_d[7:0] or cam_d[11:4]). Lines not connected must be tied low. (6) See Section 4.3.4, Processor Clocks. Copyright © 2010–2011, Texas Instruments Incorporated and Figure 6-24). PARAMETER , input pixel clock cam_pclk ...

  • Page 190

    ... Figure 6-23. CPI—Video and Graphics Digitizer—1.8-V Progressive Mode 190 Timing Requirements and Switching Characteristics ISP3 ISP2 ISP8 ISP9 D(n-2) D(n-1) D(0) Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com ISP5 ISP7 D(n-2) D(n-1) ISP10 ISP11 SWPS038-048 Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 191

    ... Input Conditions t Input signal rise time R t Input signal fall time F Output Condition C Output load capacitance LOAD (1) The load setting of the IO buffer: LB0 = 1. Copyright © 2010–2011, Texas Instruments Incorporated ISP3 ISP2 ISP5 ISP7 ISP8 ISP9 D(0) D(n–1) D(0) ISP13 EVEN 6-25) ...

  • Page 192

    ... Timing Requirements and Switching Characteristics OPP100 MIN 0.5P 0.5P 1.82 1.82 1.82 1.82 1.82 1.82 1.82 1.82 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com (4) (5) OPP50 UNIT MAX MIN MAX 75 45 MHz ...

  • Page 193

    ... Input Conditions t Input signal rise time R t Input signal fall time F Output Condition C Output load capacitance LOAD Copyright © 2010–2011, Texas Instruments Incorporated ISP16 ISP18 ISP18 ISP23 ISP24 D(n–2) D(n–1) D(0) ISP25 Table 6-22 for ISP15 and ISP16 parameters. ...

  • Page 194

    ... OPP100 MIN (2) 0.5*P (2) 0.5*P 0.5*P 3.465 0.0649*P 1.08 1.08 1.08 1.08 1.08 1.08 1.08 1.08 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com (4) (5) OPP50 UNIT MAX MIN MAX 130 65 MHz (2) 0.5*P ns (2) ...

  • Page 195

    ... Input signal rise time R t Input signal fall time F Output Condition (1) C Output load capacitance LOAD (1) The load setting of the IO buffer: LB0 = 1. Copyright © 2010–2011, Texas Instruments Incorporated ISP16 ISP4 ISP4 ISP9 D(n-2) D(n-1) D(0) ISP11 Table 6-22 for ISP15 and ISP16 parameters. ...

  • Page 196

    ... Timing Requirements and Switching Characteristics OPP100 MIN 0.5P 0.5P 1.82 1.82 1.82 1.82 1.82 1.82 1.82 1.82 1.82 1.82 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 www.ti.com (4) (5) OPP50 UNIT MAX MIN MAX 75 45 MHz (2) (2) 0 ...

  • Page 197

    ... The cam_wen signal can be used as an external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. (8) In cam_xclki, i can be equal See Figure 6-27. CPI—12-bit SYNC Normal Interlaced Copyright © 2010–2011, Texas Instruments Incorporated ISP16 ISP18 ISP18 ...

  • Page 198

    ... OPP100 OPP50 UNIT MAX MIN MAX 130 65 MHz (2) (2) 0.5P 0.5P ns (2) (2) 0.5P 0.5P ns (2) (2) 0.5*P - 0.5 3.465 6.93 0.0649*P 0.0649*P ns (2) (2) 2.27 ns 2.27 ns 2.27 ns 2.27 ns 2.27 ns 2.27 ns 2.27 ns 2.27 ns 2.27 ns 2.27 ns Copyright © 2010–2011, Texas Instruments Incorporated ...

  • Page 199

    ... Input signal rise time R t Input signal fall time F Output Condition (1) C Output load capacitance LOAD (1) The load setting of the IO buffer: LB0 = 1. Copyright © 2010–2011, Texas Instruments Incorporated ISP16 ISP4 ISP4 ISP6 ISP5 ISP7 L(n-1) D(n-2) D(n-1) D(0) ISP11 ISP14 ...

  • Page 200

    ... OPP100 OPP50 MIN MAX MIN MAX 75 45 (2) (2) 0.5P 0.5P (2) (2) 0.5P 0.5P (2) (2) 0.5*P - 0.5*P - 3.465 6.93 0.0649*P 0.0649*P (2) (2) 1.82 3.25 1.82 3.25 ISP18 ISP24 D(0) D(n-1) EOF SWPS038-054 Copyright © 2010–2011, Texas Instruments Incorporated UNIT MHz ...