SN65LVPE501RGER

Manufacturer Part NumberSN65LVPE501RGER
DescriptionIC REDRIVER/EQUALIZER 2CH 24VQFN
ManufacturerTexas Instruments
SN65LVPE501RGER datasheet
 


Specifications of SN65LVPE501RGER

Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Dual Channel x1 PCIe Redriver/Equalizer
FEATURES
1
Single Lane PCIe Equalizer/Redriver
Support for Both PCIe Gen I (2.5Gbps) and
Gen II (5.0 Gbps) Speed
Selectable Equalization, De-emphasis and
Output Swing Control
Integrated Termination
Hot-Plug Capable
Receiver Detect
Low Power:
– 330mW(TYP), V
= 3.3V
CC
Auto Low Power Modes:
– 5mW (TYP) When no Connection Detected
– 70mW (TYP) When in Auto-Low Power
Mode
DESCRIPTION
The SN65LVPE501 is a dual channel, single lane PCIe redriver and signal conditioner supporting data rates of
up to 5.0Gbps. The device complies with PCIe spec revision 2.1.
Programmable EQ, De-Emphasis and Amplitude Swing
The SN65LVPE501 is designed to minimize the signal degradation effects such as crosstalk and inter-symbol
interference (ISI) that limits the interconnect distance between two devices. The input stage of each channel
offers selectable equalization settings that can be programmed to match loss in the channel. The differential
outputs provide selectable de-emphasis to compensate for the anticipated distortion PCIe signal will experience.
Level of de-emphasis will depend on the length of interconnect and its characteristics. Both equalization and
de-emphasis levels are controlled by the setting of signal control pins EQ1, EQ2 and DE1, DE2.
To provide additional control of signal integrity in extended backplane applications LVPE501 provides
independent output amplitude control for each channel. See
Device PowerOn
Device initiates internal power-on reset after V
toggling RST pin. External reset is recommended after every device power-up. When RST is driven high, the
device samples the state of EN_RXD, if it is set H device enters Rx.Detect state where each channel will perform
Rx.Detect function (as described in PCIe spec). If EN_RXD is set L, automatic RX detect function is disabled and
both channels are enabled with their termination set to Z
Receiver Detection
While EN_RXD pin is H and device is not in sleep mode (RST is H), SN65LVPE501 performs RX.Detect on both
channels indefinitely until remote termination is detected on both channels. Automatic Rx detection feature can
be forced off by driving EN_RXD low. In this state both channels input termination are set to Z
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Check for Samples:
SN65LVPE501
Excellent Jitter and Loss Compensation
Capability:
– 30" of 6 mil Stripline on FR4
Small Foot Print – 24 Pin 4 × 4 QFN Package
High Protection Against ESD Transient
– HBM: 3,000 V
– CDM: 1,500 V
– MM: 200 V
APPLICATIONS
PC MB, Docking Stations, Backplane and
Cabled Application
Table 2
for setting details.
has stabilized. External reset can also be applied at anytime by
CC
.
DC_RX
SN65LVPE501
SLLSE30 – MAY 2010
.
DC_RX
Copyright © 2010, Texas Instruments Incorporated

SN65LVPE501RGER Summary of contents

  • Page 1

    ... HBM: 3,000 V – CDM: 1,500 V – MM: 200 V APPLICATIONS • PC MB, Docking Stations, Backplane and Cabled Application Table 2 for setting details. has stabilized. External reset can also be applied at anytime DC_RX SN65LVPE501 SLLSE30 – MAY 2010 . DC_RX Copyright © 2010, Texas Instruments Incorporated ...

  • Page 2

    ... Hi-Z. Device power is 1mW (MAX) RX-HIGH_IMP+ EID_TH exceeds max V for that channel. Exit latency is 30ns max. To use this EID_TH Product Folder Link(s): SN65LVPE501 www.ti.com diff_pp for >1µs (TYP), the associated CH will rd of normal operating power/CH Copyright © 2010, Texas Instruments Incorporated falls ...

  • Page 3

    ... Server/PC/Notebook I/O Hub R ® SN75LVPE501 Figure 1. SN65LVPE501 Typical Applications Copyright © 2010, Texas Instruments Incorporated PCIe Instrumentation Chassis /I/O expansion box/ compliant Docking Station cable Midplane Product Folder Link(s): SN65LVPE501 SN65LVPE501 SLLSE30 – MAY 2010 I/O Module I/O Module I/O Module ...

  • Page 4

    ... CHANNEL 2 OS Cntrl. OS1 Figure 2. Data Flow Block Diagram PCIe Cable System Board Mezzanine Figure 3. Typical Implementation Product Folder Link(s): SN65LVPE501 www.ti.com Detect Driver VBB_TX Receiver/ Equalizer RST# OS2 Downstream Board Card Copyright © 2010, Texas Instruments Incorporated TX1+ TX1- RX2+ RX2- ...

  • Page 5

    ... When 3-state pins are left as NC board leakage at the pin pad must be <1 µA CC otherwise drive assert mid-level state. CC Copyright © 2010, Texas Instruments Incorporated Table 1. Pin Description DESCRIPTION Non-inverting and inverting CML differential input for CH 1 and CH 2. These pins are tied to an internal voltage bias by dual termination resistor circuit. ...

  • Page 6

    ... Device not in shut_down mode 1 (default, internally pulled to Vcc) PS DEVICE FUNCTION Auto-low power mode disabled 0 (default, internally pulled to GND) 1 Auto-low power mode enabled Product Folder Link(s): SN65LVPE501 1000 875 1100 (1) OSx = 1 –4.6 dB –6.6 dB –8 DC_RX Copyright © 2010, Texas Instruments Incorporated www.ti.com ...

  • Page 7

    ... RST RX1+ RX1- GND TX2+ TX2- PART NUMBER SN65LVPE501RGER SN65LVPE501RGET (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Copyright © 2010, Texas Instruments Incorporated BOTTOM VIEW VCC ...

  • Page 8

    ... JB , using a procedure described in JESD51-2a (sections 6 and 7). JA Product Folder Link(s): SN65LVPE501 www.ti.com UNIT / VALUES –0 –0. –0 0.5 CC ±3000 V ±1500 V ±200 V See Thermal Information Table SN65LVPE501 RGE UNITS 24 PINS °C/W 0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 9

    ... Electrical Idle Detect Threshold EID_TH RL Differential Return Loss RX-DIFF RL Common Mode Return Loss RX-CM Copyright © 2010, Texas Instruments Incorporated TEST CONDITIONS RST, DEx, EQx, OSx = NC, EN_RXD = NC, K28.5 pattern at 5 Gbps 1000mV ID p-p PS=1; When auto-low power conditions are met RST = GND ...

  • Page 10

    ... MIN TYP MAX UNIT 800 1000 1200 875 mV 1100 655 495 mV 350 –3.0 –3.7 –4.0 dB –3.0 –3.7 –4.2 –6.4 dB –9.4 0.8 UI Ω 80 100 120 2.1 2.65 3 100 mVpp 100 mVpp 3.5 mV 600 280 330 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 11

    ... IN OUT t idleExit RX_1,2+ RX_1,2- t idleEntry TX_1,2+ TX_1,2- Figure 8. Auto Low Power Mode Timing (when enabled) Copyright © 2010, Texas Instruments Incorporated T diff_LH Figure 5. Propagation Delay vertical spacer V EID_TH Figure 6. Idle Mode Exit and Entry Delay vertical spacer 80% 20 Figure 7. Output Rise and Fall Times ...

  • Page 12

    ... B = End of trace on test board Figure 9. Jitter Measurement Setup vertical spacer 1-bit bits 1-bit t DE DEx = NC -3.7dB -6.4 dB DEx = 0 -9.4 dB DEx = 1 V TXDIFF_NTB_P 1000 mVpp -3.5 dB, Pattern = K28.5 ID Product Folder Link(s): SN65LVPE501 www.ti.com Jitter Measurement B AWG bits Copyright © 2010, Texas Instruments Incorporated ...

  • Page 13

    ... Output Trace Length Held Constant and Input Trace Length Varied Figure 11. Input Trace = 4 Inches, 6 mil, and Measured at Output Trace = 4 Inches Figure 12. Input Trace = 20 Inches, 6 mil, and Measured at Output Trace = 4 Inches Copyright © 2010, Texas Instruments Incorporated vertical spacer Product Folder Link(s): ...

  • Page 14

    ... SN65LVPE501 SLLSE30 – MAY 2010 Figure 13. Input Trace = 32 Inches, 6 mil, and Measured at Output Trace = 4 Inches Figure 14. Input Trace = 44 Inches, 6 mil, and Measured at Output Trace = 4 Inches 14 Submit Documentation Feedback vertical spacer Product Folder Link(s): SN65LVPE501 www.ti.com Copyright © 2010, Texas Instruments Incorporated ...

  • Page 15

    ... Variable Trace Lengths at Input and Output Figure 15. Input Trace = 28 Inches, 6 mil, and Measured at Output Trace = 24 Inches Figure 16. Input Trace = 44 Inches, 6 mil, and Measured at Output Trace = 24 Inches Copyright © 2010, Texas Instruments Incorporated vertical spacer Product Folder Link(s): SN65LVPE501 SN65LVPE501 SLLSE30 – MAY 2010 ...

  • Page 16

    ... PACKAGING INFORMATION Orderable Device (1) Package Type Package Status SN65LVPE501RGER ACTIVE VQFN SN65LVPE501RGET ACTIVE VQFN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. ...

  • Page 17

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing SN65LVPE501RGER VQFN RGE SN65LVPE501RGET VQFN RGE PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 24 3000 330.0 12.4 4.25 24 250 180.0 12.4 4.25 Pack Materials-Page 1 ...

  • Page 18

    ... Device Package Type SN65LVPE501RGER VQFN SN65LVPE501RGET VQFN PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) RGE 24 3000 RGE 24 250 Pack Materials-Page 2 6-Sep-2010 Width (mm) Height (mm) 346.0 346.0 29.0 190.5 212.7 31.8 ...

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    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...