MC74HC367ADTR2G ON Semiconductor, MC74HC367ADTR2G Datasheet

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MC74HC367ADTR2G

Manufacturer Part Number
MC74HC367ADTR2G
Description
IC BUFFER 3ST HEX 16-TSSOP
Manufacturer
ON Semiconductor
Datasheet

Specifications of MC74HC367ADTR2G

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
MC74HC367A
Hex 3−State Noninverting
Buffer with Separate 2−Bit
and 4−Bit Sections
High−Performance Silicon−Gate CMOS
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
own active−low Output Enable. When either of the enables is high, the
affected buffer outputs are placed into high−impedance states. The
HC367A has noninverting outputs.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 2
The MC74HC367A is identical in pinout to the LS367. The device
This device is arranged into 2−bit and 4−bit sections, each having its
No. 7A
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 μA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
Chip Complexity: 92 FETs or 23 Equivalent Gates
OUTPUT ENABLE 1
OUTPUT ENABLE 2
15
1
A0
A1
A2
A3
A4
A5
LOGIC DIAGRAM
10
12
14
2
4
6
PIN 16 = V
PIN 8 = GND
13
11
3
5
7
9
Y0
Y1
Y2
Y3
Y4
Y5
CC
1
ENABLE 1
OUTPUT
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
X = don’t care
Z = high impedance
Enable 1,
Enable 2
ORDERING INFORMATION
GND
A0
Y0
A1
Y1
A2
Y2
http://onsemi.com
FUNCTION TABLE
PIN ASSIGNMENT
H
L
L
Inputs
1
2
3
4
5
6
7
8
PLASTIC PACKAGE
A
H
Publication Order Number:
X
L
TSSOP PACKAGE
SOIC PACKAGE
CASE 751B−05
CASE 948F−01
CASE 648−08
DT SUFFIX
N SUFFIX
D SUFFIX
16
15
14
13
12
11
10
16−LEAD
16−LEAD
16−LEAD
9
Output
Plastic
SOIC
TSSOP
Y
H
L
Z
MC74HC367A/D
V
OUTPUT
ENABLE 2
A5
Y5
A4
Y4
A3
Y3
CC

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MC74HC367ADTR2G Summary of contents

Page 1

MC74HC367A Hex 3−State Noninverting Buffer with Separate 2−Bit and 4−Bit Sections High−Performance Silicon−Gate CMOS The MC74HC367A is identical in pinout to the LS367. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL ...

Page 2

MAXIMUM RATINGS* Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 3

DC ELECTRICAL CHARACTERISTICS Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 4

INPUT A 50% 10% t PLH 90% 50% OUTPUT Y 10% t TLH Figure 1. TEST POINT OUTPUT DEVICE UNDER C TEST *Includes all probe and jig capacitance Figure 3. A OUTPUT ENABLE SWITCHING WAVEFORMS t OUTPUT ...

Page 5

− 0.25 (0.010) M −A − −B − −T − SEATING PLANE 0.25 (0.010) T ...

Page 6

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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