TXRX TRANSLATING 3ST XSON8U

74LVC2T45GD,125

Manufacturer Part Number74LVC2T45GD,125
DescriptionTXRX TRANSLATING 3ST XSON8U
ManufacturerNXP Semiconductors
74LVC2T45GD,125 datasheet
 


Specifications of 74LVC2T45GD,125

Logic Family74LVCNumber Of Channels Per Chip2
Propagation Delay Time15.2 nsSupply Voltage (max)5.5 V
Supply Voltage (min)1.2 VMaximum Operating Temperature+ 125 C
Package / CaseXSON-8UMaximum Power Dissipation250 mW
Minimum Operating Temperature- 40 CMounting StyleSMD/SMT
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names568-5480-2
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74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
Rev. 4 — 20 August 2010
1. General description
The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with
3-state outputs that enable bidirectional level translation. They feature two data
input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (V
and V
CC(B)
5.5 V making the device suitable for translating between any of the low voltage nodes
(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins nA and DIR are referenced to V
pins nB are referenced to V
LOW on DIR allows transmission from nB to nA.
The devices are fully specified for partial power-down applications using I
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either V
GND level, both A port and B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH2T45 holds unused or floating data inputs at a valid
logic level.
2. Features and benefits
Wide supply voltage range:
V
V
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 4000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Maximum data rates:
420 Mbps (3.3 V to 5.0 V translation)
210 Mbps (translate to 3.3 V))
140 Mbps (translate to 2.5 V)
75 Mbps (translate to 1.8 V)
60 Mbps (translate to 1.5 V)
). Both V
and V
can be supplied at any voltage between 1.2 V and
CC(A)
CC(B)
. A HIGH on DIR allows transmission from nA to nB and a
CC(B)
: 1.2 V to 5.5 V
CC(A)
: 1.2 V to 5.5 V
CC(B)
Product data sheet
CC(A)
and
CC(A)
. The I
OFF
OFF
or V
are at
CC(A)
CC(B)

74LVC2T45GD,125 Summary of contents

  • Page 1

    Dual supply translating transceiver; 3-state Rev. 4 — 20 August 2010 1. General description The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two data input-output ports ...

  • Page 2

    ... NXP Semiconductors Suspend mode Latch-up performance exceeds 100 mA per JESD 78 Class II ±24 mA output drive (V Inputs accept voltages up to 5.5 V Low power consumption: 16 μA maximum I I OFF Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1 ...

  • Page 3

    ... NXP Semiconductors Table 2. Marking …continued Type number 74LVC2T45GN 74LVCH2T45GN 74LVC2T45GS 74LVCH2T45GS [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 5 DIR CC(A) Fig 1. Logic symbol 6. Pinning information 6.1 Pinning 74LVC2T45 74LVCH2T45 V 1 CC( GND 001aai904 Fig 3 ...

  • Page 4

    ... NXP Semiconductors 74LVC2T45 74LVCH2T45 V 1 CC( GND 4 Transparent top view Fig 5. Pin configuration SOT996-2 6.2 Pin description Table 3. Pin description Symbol Pin SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 V 1 CC( GND 4 DIR CC(B) 7. Functional description [1] Table 4. Function table Supply voltage Input DIR ...

  • Page 5

    ... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage A CC(A) V supply voltage B CC(B) I input clamping current IK V input voltage I I output clamping current OK V output voltage ...

  • Page 6

    ... NXP Semiconductors 10. Static characteristics Table 7. Typical static characteristics recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I bus hold LOW current BHL I bus hold HIGH current BHH ...

  • Page 7

    ... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level data input IH input voltage V CCI V CCI V CCI V CCI V CCI DIR input V CCI V CCI V CCI V CCI V CCI V LOW-level data input IL input voltage V CCI V CCI ...

  • Page 8

    ... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V LOW-level output voltage = 100 μ CCO input leakage DIR input current 5.5 V CCI I bus hold LOW port BHL current ...

  • Page 9

    ... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I power-off A port; V OFF leakage V CC(A) current V CC(B) B port CC(B) V CC(A) I supply current A port CC(A) V CC(A) V CC(A) V CC(A) B port CC(A) V CC(A) V CC(B) V CC(B) A plus B port ( ...

  • Page 10

    ... NXP Semiconductors 11. Dynamic characteristics Table 9. Typical dynamic characteristics at V Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter t LOW to HIGH PLH propagation delay t HIGH to LOW PHL propagation delay t HIGH to OFF-state PHZ propagation delay t LOW to OFF-state PLZ propagation delay ...

  • Page 11

    ... NXP Semiconductors Table 11. Typical power dissipation capacitance at V Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions C power dissipation A port: (direction A to B); PD capacitance B port: (direction port: (direction B to A); B port: (direction [ used to determine the dynamic power dissipation (P PD × V × f × ...

  • Page 12

    ... NXP Semiconductors Dynamic characteristics for temperature range −40 °C to +85 °C Table 12. Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t OFF-state to HIGH DIR to A PZH propagation delay DIR OFF-state to LOW DIR to A PZL propagation delay DIR ...

  • Page 13

    ... NXP Semiconductors Dynamic characteristics for temperature range −40 °C to +85 °C Table 12. Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t LOW to OFF-state DIR to A PLZ propagation delay DIR OFF-state to HIGH DIR to A PZH propagation delay DIR to B ...

  • Page 14

    ... NXP Semiconductors Dynamic characteristics for temperature range −40 °C to +125 °C Table 13. Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t OFF-state to LOW DIR to A PZL propagation delay DIR 2 2.7 V CC(A) t LOW to HIGH PLH propagation delay HIGH to LOW ...

  • Page 15

    ... NXP Semiconductors Dynamic characteristics for temperature range −40 °C to +125 °C Table 13. Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t OFF-state to HIGH DIR to A PZH propagation delay DIR OFF-state to LOW DIR to A PZL propagation delay DIR to B ...

  • Page 16

    ... NXP Semiconductors Table 14. Measurement points Supply voltage Input CC(A) CC( 1.6 V 0.5V 1. 2.7 V 0.5V 3 5.5 V 0.5V [ the supply voltage associated with the data input port. CCI [ the supply voltage associated with the output port. CCO Test data is given in Table R = Load resistance. ...

  • Page 17

    ... NXP Semiconductors 13. Typical propagation delay characteristics 14 t PHL (ns HIGH to LOW propagation delay ( PHL (ns HIGH to LOW propagation delay ( ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) ( 5.0 V. CC(B) Fig 10. Typical propagation delay versus load capacitance; T 74LVC_LVCH2T45 Product data sheet 74LVC2T45; 74LVCH2T45 ...

  • Page 18

    ... NXP Semiconductors 14 t PHL (ns HIGH to LOW propagation delay ( PHL (ns HIGH to LOW propagation delay ( ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) ( 5.0 V. CC(B) Fig 11. Typical propagation delay versus load capacitance; T 74LVC_LVCH2T45 Product data sheet 74LVC2T45; 74LVCH2T45 001aai911 14 t PLH ...

  • Page 19

    ... NXP Semiconductors 14 t PHL (ns HIGH to LOW propagation delay ( PHL (ns HIGH to LOW propagation delay ( ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) ( 5.0 V. CC(B) Fig 12. Typical propagation delay versus load capacitance; T 74LVC_LVCH2T45 Product data sheet 74LVC2T45; 74LVCH2T45 001aai915 14 t PLH ...

  • Page 20

    ... NXP Semiconductors 14 t PHL (ns HIGH to LOW propagation delay ( PHL (ns HIGH to LOW propagation delay ( ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) ( 5.0 V. CC(B) Fig 13. Typical propagation delay versus load capacitance; T 74LVC_LVCH2T45 Product data sheet 74LVC2T45; 74LVCH2T45 001aai919 14 t PLH ...

  • Page 21

    ... NXP Semiconductors 14 t PHL (ns HIGH to LOW propagation delay ( PHL (ns HIGH to LOW propagation delay ( ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) ( 5.0 V. CC(B) Fig 14. Typical propagation delay versus load capacitance; T 74LVC_LVCH2T45 Product data sheet 74LVC2T45; 74LVCH2T45 001aai923 14 t PLH ...

  • Page 22

    ... NXP Semiconductors 14 t PHL (ns HIGH to LOW propagation delay ( PHL (ns HIGH to LOW propagation delay ( ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) ( 5.0 V. CC(B) Fig 15. Typical propagation delay versus load capacitance; T 74LVC_LVCH2T45 Product data sheet 74LVC2T45; 74LVCH2T45 001aai927 14 t PLH ...

  • Page 23

    ... NXP Semiconductors 14. Application information 14.1 Unidirectional logic level-shifting application The circuit given unidirectional logic level-shifting application. V CC1 V CC1 system-1 Fig 16. Unidirectional logic level-shifting application Table 16. Description of unidirectional logic level-shifting application Pin Name Function CC(A) CC1 2 1A OUT 3 2A OUT 4 GND GND ...

  • Page 24

    ... NXP Semiconductors V CC1 I/O-1 PULL-UP/DOWN DIR CTRL system-1 Pull-up or pull-down only needed for 74LVC2T45. Fig 17. Bidirectional logic level-shifting application Table 17 and then from system-2 to system-1. Table 17. Description of bidirectional logic level-shifting application State DIR CTRL I/O output input [ HIGH voltage level LOW voltage level; ...

  • Page 25

    ... NXP Semiconductors 14.4 Enable times Calculate the enable times for the 74LVC2T45; 74LVCH2T45 using the following formulas: • t PZH • t PZL • t PZH • t PZL In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the 74LVC2T45; ...

  • Page 26

    ... NXP Semiconductors 15. Package outline VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

  • Page 27

    ... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

  • Page 28

    ... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1. 0.5 mm terminal 1 index area (2) (4× terminal 1 index area Dimensions (1) Unit max 0.5 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

  • Page 29

    ... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 21. Package outline SOT996-2 (XSON8U) ...

  • Page 30

    ... NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 ...

  • Page 31

    ... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.25 mm nom 0.15 1.20 min 0.12 1.15 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

  • Page 32

    ... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

  • Page 33

    ... NXP Semiconductors 16. Abbreviations Table 19. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 17. Revision history Table 20. Revision history Document ID Release date 74LVC_LVCH2T45 v.4 20100820 • Modifications: Added type number 74LVC2T45GF (SOT1089/XSON8 package). ...

  • Page 34

    ... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

  • Page 35

    ... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 19. Contact information For more information, please visit: For sales office addresses, please send an email to: 74LVC_LVCH2T45 Product data sheet 74LVC2T45 ...

  • Page 36

    ... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 10 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 13 Typical propagation delay characteristics ...