74LVC2T45DC,125 NXP Semiconductors, 74LVC2T45DC,125 Datasheet - Page 12

• Manufacturer Part Number: 74LVC2T45DC,125
• Description: TXRX TRANSLATING 3ST 8VSSOP
• Manufacturer: NXP Semiconductors

Specifications of 74LVC2T45DC,125

• Logic Family: 74LVC
• Number Of Channels Per Chip: 2
• Propagation Delay Time: 15.2 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.2 V
• Maximum Operating Temperature: + 125 C
• Package / Case: VSSOP-8
• Maximum Power Dissipation: 250 mW
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-5479-2

NXP Semiconductors
Table 12.
Voltages are referenced to GND (ground = 0 V); for test circuit see
74LVC_LVCH2T45
Product data sheet
Symbol Parameter
t
t
V
t
t
t
t
t
t
V
t
t
t
t
t
t
V
t
t
t
PZH
PZL
PLH
PHL
PHZ
PLZ
PZH
PZL
PLH
PHL
PHZ
PLZ
PZH
PZL
PLH
PHL
PHZ
CC(A)
CC(A)
CC(A)
= 2.3 V to 2.7 V
= 3.0 V to 3.6 V
= 4.5 V to 5.5 V
OFF-state to HIGH
propagation delay
OFF-state to LOW
propagation delay
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
HIGH to OFF-state
propagation delay
LOW to OFF-state
propagation delay
OFF-state to HIGH
propagation delay
OFF-state to LOW
propagation delay
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
HIGH to OFF-state
propagation delay
LOW to OFF-state
propagation delay
OFF-state to HIGH
propagation delay
OFF-state to LOW
propagation delay
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
HIGH to OFF-state
propagation delay
Dynamic characteristics for temperature range −40 °C to +85 °C
Conditions
DIR to A
DIR to B
DIR to A
DIR to B
A to B
B to A
A to B
B to A
DIR to A
DIR to B
DIR to A
DIR to B
DIR to A
DIR to B
DIR to A
DIR to B
A to B
B to A
A to B
B to A
DIR to A
DIR to B
DIR to A
DIR to B
DIR to A
DIR to B
DIR to A
DIR to B
A to B
B to A
A to B
B to A
DIR to A
DIR to B
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
All information provided in this document is subject to legal disclaimers.
1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V
Min
2.3
2.0
2.3
1.8
2.1
3.0
1.7
2.3
2.3
1.7
2.2
1.7
2.3
2.9
2.0
2.3
2.2
1.6
2.3
1.7
1.7
2.9
-
-
-
-
-
-
-
-
-
-
-
-
Rev. 4 — 20 August 2010
Max
35.2
29.6
39.4
34.4
17.9
13.5
15.8
22.5
14.6
28.1
23.7
34.3
23.9
17.1
15.6
10.9
18.0
13.6
25.4
22.7
28.9
22.9
16.6
10.5
15.3
10.8
17.3
11.8
11.8
8.1
5.8
7.3
5.6
5.4
Min
3.0
2.3
2.2
2.1
1.9
2.1
1.7
2.5
2.1
1.7
2.0
1.8
2.3
2.9
2.0
2.4
1.9
1.4
1.8
1.7
1.7
2.9
-
-
-
-
-
-
-
-
-
-
-
-
74LVC2T45; 74LVCH2T45
Figure
Max
33.7
28.2
36.2
31.4
16.0
12.9
21.4
13.2
22.5
21.8
29.9
21.0
15.5
12.6
16.5
12.5
19.7
21.1
23.6
19.9
15.1
12.2
16.1
9.3
8.5
8.1
5.8
7.2
7.1
7.3
5.6
6.8
7.0
5.4
Dual supply translating transceiver; 3-state
9; for wave forms see
Min
2.5
1.5
1.5
1.4
1.4
2.1
1.7
2.0
1.4
1.3
1.3
1.3
2.3
2.3
2.0
1.9
1.0
1.0
1.0
0.9
1.7
2.3
-
-
-
-
-
-
-
-
-
-
-
-
V
CC(B)
…continued
Max
25.2
19.8
24.4
25.6
17.5
14.3
18.5
15.6
10.1
14.0
13.6
15.5
14.3
11.0
8.5
8.5
7.5
7.5
8.1
5.8
9.0
8.0
6.2
7.0
5.4
7.3
5.6
7.8
7.5
4.8
6.2
4.6
5.4
9.7
Min
1.3
1.4
1.3
1.3
2.1
2.8
1.7
2.5
0.8
0.7
0.8
0.8
2.3
2.7
2.0
2.3
0.7
0.7
0.7
0.7
1.7
2.7
-
-
-
-
-
-
-
-
-
-
-
-
Figure 7
23.9
17.7
22.9
24.2
16.4
12.0
16.3
13.5
12.7
13.6
12.3
Max
11.2
6.2
8.0
5.4
7.0
8.1
9.3
5.8
8.4
5.6
5.6
5.0
5.0
7.3
8.6
5.6
7.1
5.4
4.4
4.5
4.0
5.4
8.0
© NXP B.V. 2010. All rights reserved.
and
Min
1.1
1.0
0.9
0.9
2.1
2.3
1.7
1.8
0.7
0.6
0.7
0.7
2.7
2.2
2.0
1.7
0.5
0.5
0.5
0.5
1.7
2.5
-
-
-
-
-
-
-
-
-
-
-
-
Figure
Max
22.2 ns
17.3 ns
20.4 ns
24.1 ns
13.3 ns
10.6 ns
13.1 ns
12.7 ns
10.3 ns
10.0 ns
10.8 ns
11.3 ns
4.8
7.5
4.6
6.2
8.1
6.9
5.8
5.8
4.4
5.4
4.0
4.5
7.3
6.3
5.6
4.9
3.9
3.9
3.5
3.5
5.4
5.7
8.
12 of 36
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns