74LVC2T45GT,115 NXP Semiconductors, 74LVC2T45GT,115 Datasheet - Page 15

• Manufacturer Part Number: 74LVC2T45GT,115
• Description: TXRX TRANSLATING 3ST XSON8
• Manufacturer: NXP Semiconductors

Specifications of 74LVC2T45GT,115

• Logic Family: 74LVC
• Number Of Channels Per Chip: 2
• Propagation Delay Time: 15.2 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.2 V
• Maximum Operating Temperature: + 125 C
• Package / Case: XSON-8
• Maximum Power Dissipation: 250 mW
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-5482-2

NXP Semiconductors
Table 13.
Voltages are referenced to GND (ground = 0 V); for test circuit see
[1]
12. Waveforms
74LVC_LVCH2T45
Product data sheet
Symbol Parameter
t
t
PZH
PZL
Fig 7.
Fig 8.
t
PZH
and t
OFF-state to HIGH
propagation delay
OFF-state to LOW
propagation delay
Measurement points are given in
V
Measurement points are given in
V
The data input (A, B) to output (B, A) propagation delay times
Enable and disable times
OL
OL
Dynamic characteristics for temperature range −40 °C to +125 °C
PZL
and V
and V
are calculated values using the formula shown in
OH
OH
are typical output voltage levels that occur with the output load.
are typical output voltage levels that occur with the output load.
HIGH-to-OFF
OFF-to-HIGH
LOW-to-OFF
OFF-to-LOW
DIR input
output
output
Conditions
DIR to A
DIR to B
DIR to A
DIR to B
nB, nA output
nA, nB input
V
GND
GND
Table
Table
V
CCO
V
OH
[1]
[1]
[1]
[1]
OL
V
All information provided in this document is subject to legal disclaimers.
I
1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V
GND
14.
14.
V
Min
V
OH
OL
-
-
-
-
V
I
Rev. 4 — 20 August 2010
V
enabled
outputs
M
Max
26.1
22.4
31.0
22.9
t
PLZ
t
PHZ
V
M
Section 14.4 “Enable
Min
V
V
X
-
-
-
-
M
t
V
PHL
74LVC2T45; 74LVCH2T45
Y
Figure
Max
20.9
20.8
25.5
19.5
disabled
outputs
Dual supply translating transceiver; 3-state
9; for wave forms see
Min
-
-
-
-
V
times”.
t
CC(B)
PZL
t
001aaj644
PZH
t
PLH
…continued
Max
13.5
12.4
15.8
12.9
V
M
V
001aae968
M
outputs
enabled
Min
-
-
-
-
Figure 7
Max
12.6
10.1
13.2
11.0
© NXP B.V. 2010. All rights reserved.
and
Min
-
-
-
-
Figure
Max
10.2 ns
9.3
8.4
9.9
8.
15 of 36
Unit
ns
ns
ns